PCM codec and modem for 56K bi-directional transmission

Claim 2

An enhanced codec apparatus, comprising: a digital signal processor circuit; a digital interface port with a first coupling to said digital signal processor circuit and a second coupling to a digital network; a digital conversion subsystem comprising a DAC wherein said DAC has a digital input coupled to receive a digitally encoded signal sample derived from said digital interface port and an analog output coupled to a first analog signal port, said digital conversion subsystem also comprising an ADC that has a digital output and an analog input; an echo canceller processing module comprising an adaptive filter and a differential amplifier, said echo canceller processing module controllably coupled to said digital signal processing circuit and opertively coupled to receive at an X-input to said adaptive filter a digital representation of a signal derived from said digital interface port, said echo canceller processing module also operatively coupled to receive at a first input to said differential amplifier, a signal that passes through a second analog signal port, the output of said differential amplifier being coupled to said analog input of said ADC, said echo canceller processing module operative to cancel an echo component which leaks from the output of said first analog signal port back into the input of said second analog signal port when said first and second analog signal ports are coupled to a subscriber line; a pulse decoder processing module controllably coupled to said digital signal processing circuit and having an input operatively coupled to the output of said ADC, said pulse decoder processing module operative to regenerate a PCM data stream; wherein the output of said adaptive filter is fed through a second DAC, and a second input of said differential amplifier is coupled to the output of said second DAC.

Claim 3

The enhanced codec apparatus according to claim 1 , wherein high-speed communications involves a data rate from 33.6 kbps to 56 kbps.

Claim 4

The enhanced codec apparatus according to claim 1 , further comprising a chip carrier package which is pin-compatible with an existing PCM codec, whereby an existing line card can be upgraded to an enhanced line card by replacing said existing codec with said enhanced codec.

Claim 5

The enhanced codec apparatus according to claim 1 , further comprising an out-of-band DSL processing circuit for processing DSL modem signals.

Claim 6

The enhanced codec according to claim 1 , wherein said ADC samples its input at a first sample rate higher than a second sample rate employed by said digital interface.

Claim 7

The enhanced codec apparatus according to claim 1 , further comprising: a protocol detect processing module controllably coupled to said digital signal processing circuit, said protocol detect processing module operative to detect a transmission protocol used within said POTS portion of said subscriber line and select a pulse decoder mapping operation in response thereto.

Claim 8

The enhanced codec apparatus according to claim 6 , wherein said protocol detect module is further operative to detect an echo canceller training phase in said protocol and said enhanced codec further comprises: an echo canceller training module controllably coupled to said digital signal processing circuit and operatively coupled to receive the detection output of said protocol detect module, said echo canceller training module operative train said echo canceller when an echo canceller training phase is detected by said protocol detect processing module.

Claim 9

The enhanced codec apparatus according to claim 6 , wherein said protocol detect module is further operative to detect a subscriber line equalizer training phase in said protocol and said enhanced codec further comprises: an equalizer processing module controllably coupled to said digital signal processing circuit and operatively coupled to receive the detection output of said protocol detect module and having an output operatively coupled to the input of said pulse decoder.

Claim 10

The enhanced codec apparatus according to claim 8 , wherein said ADC samples its input at a first sample rate higher than a second sample rate employed by said digital interface, and said equalizer and pulse decoder processing modules process information at said first sample rate to produce a reencoded output at said second sample rate.

Claim 11

The enhanced codec apparatus according to claim 6 , further comprising: a programmable instruction memory; wherein said protocol detect module detects a management protocol sequence and responds thereto by loading a new program instruction into said instruction memory.

Claim 12

The enhanced codec apparatus according to claim 1 , further comprising: a first filter interposed between the analog output of said DAC and said first analog signal port; and a second filter interposed between said second analog signal port and the analog input of said ADC.

Claim 13

The enhanced codec apparatus according to claim 1 , further comprising said line interface circuit.

Claim 14

The enhanced codec apparatus according to claim 12 , further comprising a line card.

Claim 15

The enhanced codec apparatus according to claim 13 , further comprising a network interface equipment rack into which are plugged at least one of said line cards.

Claim 16

An enhanced codes apparatus comprising: a digital to analog converter; an analog-to-digital converter; a mapping function module; and an echo canceller with an X-input coupled to the input of the digital-to-analog converter and a D-input coupled to the output of the analog-to-digital converter, said echo canceller operative to cancel an echo component leaking from the output of said digital-to-analog converter back to the input of the analog-to-digital converter; a second digital-to-analog converter; and a differential amplifier circuit with a first differential input coupled to a line interface circuit and a second differential input coupled to the output of said second digital-to-analog converter, the output of said differential amplifier operatively coupled to the input of said analog-to-digital converter, said differential amplifier circuit operative to cancel said echo component prior to conversion by said analog-to-digital converter; wherein said mapping function module is operative to selectively convert a digital representation of an uplink-analog signal to one of a PCM waveform representation and a decoded bit stream inserted into a PCM data stream.

Claim 17

An enhanced codes apparatus comprising: a digital to analog converter; an analog-to-digital converter; a mapping function module; and an echo canceller with an X-input coupled to the input of the digital-to-analog converter and a D-input coupled to the output of the analog-to-digital converter, said echo canceller operative to cancel an echo component leaking from the output of said digital-to-analog converter back to the input of the analog-to-digital converter; a second digital-to-analog converter; and a differential amplifier circuit with a first differential input coupled to a line interface circuit and a second differential input coupled to the output of said second digital-to-analog converter, the output of said differential amplifier operatively coupled to the input of said analog-to-digital converter, said differential amplifier circuit operative to cancel said echo component prior to conversion by said analog-to-digital converter; wherein said mapping function module is operative to selectively convert a digital representation of an uplink-analog signal to one of a PCM waveform representation and a decoded bit stream inserted into a PCM data stream.

Claim 18

The apparatus of claim 15 , further comprising: a protocol detection module operative to detect whether said apparatus is being used for a high-speed uplink modem connection or a voice connection, and if said codec is used in a modem connection, to perform signal conditioning to recover a high-speed uplink bit stream, encode said high-speed uplink bit stream into a PCM data stream, and transmit said PCM data stream to a digital network.

Claim 19

The codec of claim 15 , wherein said mapping function module further comprises a digital impairment compensation module.

Claim 20

The codec of claim 15 , wherein said analog-to-digital converter uses a 16-bit linear format and samples at a sampling rate greater than 8000 Hz, and the mapping function module performs equalization, clock recovery, downsampling and pulse decoding to produce said PCM data stream.

Claim 23

The subscriber modem apparatus of claim 19 , further comprising: a protocol module operative to transmit a training signal to said enhanced codec to allow said enhanced codec to configure a set of signal processing parameters contained therein.

Claim 24

The enhanced codec apparatus of claim 1 , wherein the enhanced codec is for use in a network interface line card; and wherein said PCM data stream is coupled for transmission to said digital network via said digital interface, and said enhanced codec thereby enables high-speed digital communication in an uplink direction a using a POTS channel of a subscriber line.

Claim 25

An enhanced codec apparatus for use in a network interface line card, comprising: a digital signal processor circuit; a digital interface port with a first coupling to said digital signal processor circuit and a second coupling to a digital network; a digital conversion subsystem comprising a DAC wherein said DAC has a digital input coupled to receive a digitally encoded signal sample derived from said digital interface port and an analog output coupled to a first analog signal port, said digital conversion subsystem also comprising an ADC that has a digital output and an analog input; an echo canceller processing module comprising an adaptive filter and a differential amplifier, said echo canceller processing module controllably coupled to said digital signal processing circuit and operatively coupled to receive at an X-input to said adaptive filter a digital representation of a signal derived from said digital interface port said echo canceller processing module also operatively coupled to receive at a first input to said differential amplifier, a signal that passes through a second analog signal port, the output of said differential amplifier being coupled to said analog input of said ADC, said echo canceller processing module operative to cancel an echo component which leaks from the output of said first analog signal port back into the input of said second analog signal port when said first and second analog signal ports are coupled to a subscriber line; a pulse decoder processing module controllably coupled to said digital signal processing circuit and having an input operatively coupled to the output of said ADC, said pulse decoder processing module operative to regenerate a PCM data stream; wherein said PCM data stream is coupled for transmission to said digital network via said digital interface, and said enhanced code thereby enables high-speed digital communication in an uplink direction using a POTS channel of a subscriber line; and wherein the output of said adaptive fitter is fed through a second DAC, and a second input of said differential amplifier is coupled to the output of said second DAC.

Claim 26

An enhanced codec apparatus for use in a network interface line card, comprising: a digital signal processor circuit; a digital interface port with a first coupling to said digital signal processor circuit and a second coupling to a digital network; a digital conversion subsystem comprising a DAC wherein said DAC has a digital input coupled to receive a digitally encoded signal sample derived from said digital interface port and an analog output coupled to a first analog signal port, said digital conversion subsystem also comprising an ADC that has a digital output and an analog input; an echo canceller processing module comprising an adaptive filter and a differential amplifier, said echo canceller processing module controllably coupled to said digital signal processing circuit and operatively coupled to receive at an X-input to said adaptive filter a digital representation of a signal derived from said digital interface port said echo canceller processing module also operatively coupled to receive at a first input to said differential amplifier, a signal that passes through a second analog signal port, the output of said differential amplifier being coupled to said analog input of said ADC, said echo canceller processing module operative to cancel an echo component which leaks from the output of said first analog signal port back into the input of said second analog signal port when said first and second analog signal ports are coupled to a subscriber line; a pulse decoder processing module controllably coupled to said digital signal processing circuit and having an input operatively coupled to the output of said ADC, said pulse decoder processing module operative to regenerate a PCM data stream; wherein said PCM data stream is coupled for transmission to said digital network via said digital interface, and said enhanced code thereby enables high-speed digital communication in an uplink direction using a POTS channel of a subscriber line; and wherein the output of said adaptive fitter is fed through a second DAC, and a second input of said differential amplifier is coupled to the output of said second DAC.

Claim 27

The enhanced codec apparatus according to claim 22 , wherein said echo canceller is trained using an FXLMS algorithm.

Claim 28

The subscriber modem apparatus of claim 19 , whereby the uplink data transmitter is capable of operating in a mode where it transmits pulse data to the enhanced codec to provide an uplink data rate selected between 53 kbps and 64 kbps.