US6521485B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for manufacturing wafer level chip size package
Assignee: Walsin Advanced Electronics Ltd
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Filing: 2001-01-17
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Granted: 2003-02-18
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Expires: 2021-01-17
Abstract
Abstract A method for manufacturing a wafer level chip size package and the method comprises the steps of: securing wafer to a partly etched lead frame, drilling blind hole and filling conductive material after packaging the lead frame to electrically connect the lead frame and the wafer, thus providing inner electrical connection of the wafer after packaging.
Inventors
- 👤 Spencer Su
- 👤 James Lai
- 👤 Lin Chien-Tsun
- 👤 Captain Chen
- 👤 Allen Chen
- 👤 C.S. Yang
- 👤 Chang Chao-Chia
- 👤 Kevin Hsia
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:56
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/10; H10W74/111; H10W74/129; H10W70/00; H10W70/60; H10W70/62; H10W70/65; H10W70/654; H10W70/656; H10W72/00; H10W72/01; H10W72/019; H10W72/90; H10W72/921; H10W72/922; H10W72/923; H10W72/941; H10W72/9415; H10W72/944; H10W72/9445; H10W74/15; H10W90/00; H10W90/701; H10W90/721; H10W90/724; H10W90/731; H10W90/734
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
238 words
A method for manufacturing wafer level chip size package at least comprising the steps of: providing a wafer having a plurality of chips, each chip having a plurality of connecting pads on its active surface; providing a metal plate consisting of a first layer and a second layer, wherein a plurality of conductive circuits are formed on the first layer of the metal plate by selectively etching, the plurality of conductive circuits are fixed on the second layer of the metal plate, and each conductive circuit has at least a first end and a second end, and the first ends of the conductive circuits are corresponding to the connecting pads of the chips in the wafer; securing the active surfaces of the chips onto the first layer of the metal plate, when the wafer and the metal plate being secured, connecting pads of the chips and the first ends of the conductive circuits being in vertical position to each other; drilling a plurality of blind holes on the plurality of first ends, wherein the blind holes pass through the metal plate and extend until exposing the connecting pads of the wafer; filling conductive material on the plurality of blind holes until the connecting pads of chip and the first ends of the conductive circuits becoming electrical connection; removing the second layer of the metal plate; and dicing the packed wafer to form a plurality of chip size packages.
Claim 2
Independent Claim
238 words
A method for manufacturing wafer level chip size package at least comprising the steps of: providing a wafer having a plurality of chips, each chip having a plurality of connecting pads on its active surface; providing a metal plate consisting of a first layer and a second layer, wherein a plurality of conductive circuits are formed on the first layer of the metal plate by selectively etching, the plurality of conductive circuits are fixed on the second layer of the metal plate, and each conductive circuit has at least a first end and a second end, and the first ends of the conductive circuits are corresponding to the connecting pads of the chips in the wafer; securing the active surfaces of the chips onto the first layer of the metal plate, when the wafer and the metal plate being secured, connecting pads of the chips and the first ends of the conductive circuits being in vertical position to each other; drilling a plurality of blind holes on the plurality of first ends, wherein the blind holes pass through the metal plate and extend until exposing the connecting pads of the wafer; filling conductive material on the plurality of blind holes until the connecting pads of chip and the first ends of the conductive circuits becoming electrical connection; removing the second layer of the metal plate; and dicing the packed wafer to form a plurality of chip size packages.
Claim 3
Dependent Claim
42 words
The method for manufacturing a wafer level chip size package in accordance with claim 1 , wherein, after the step of removing the second layer of the metal plate, further comprises: planting solder balls on the second ends of the conductive circuits.
Claim 4
Dependent Claim
33 words
The method for manufacturing a wafer level chip size package in accordance with claim 1 , wherein, before the step of filling conductive material, further comprises: coating metal foil inside said blind holes.
Claim 5
Dependent Claim
35 words
The method for manufacturing a wafer level chip size package in accordance with claim 1 , wherein in step of providing a metal plate, the surface of the first layer of metal plate is rough.
Claim 6
Dependent Claim
40 words
The method for manufacturing a wafer level chip size package in accordance with claim 1 , wherein the minimum distance between a plurality of the second ends is longer than the minimum distance between a plurality of the first ends.
Claim 7
Dependent Claim
35 words
The method for manufacturing a wafer level chip size package in accordance with claim 1 , wherein each blind hole has a smaller area on the corresponding first end than area of the first end.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2006-02-17 | 2006-08-19 | 2007-02-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-02-17 | 2010-08-19 | 2011-02-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-02-17 | 2014-08-19 | 2015-02-18 | $7700.00 | Window Closed / Lapsed |