Patent US6519706B1 successfully refreshed from Google Patents.
US6519706B1
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DSP control apparatus and method for reducing power consumption
Assignee: NEC Corp
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Filing: 1999-10-05
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Granted: 2003-02-11
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Expires: 2019-10-05
Abstract
Abstract A digital signal processor (DSP) control apparatus includes a DSP, estimation unit, calculation unit, and clock generator. The DSP performs digital signal arithmetic processing using a clock having a variable frequency. The estimation unit estimates an arithmetic processing amount of the DSP. The calculation unit calculates a new clock frequency on the basis of an estimated arithmetic processing amount from the estimation unit. The clock generator supplies a clock having a frequency calculated by the calculation unit to the DSP.
Inventors
- 👤 Kazuo Ogoro
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:16
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/324; G06F7/00; G06F7/38; G06F7/48; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
80 words
A digital signal processor (DSP) control apparatus comprising: an arithmetic processing means for performing digital signal arithmetic processing using a clock having a variable frequency; estimating means for estimating an arithmetic processing amount of said arithmetic processing means; calculation means for calculating a new clock frequency on the basis of an estimated arithmetic processing amount from said estimation means; and clock supply means for supplying a clock having a frequency calculated by said calculation means to said arithmetic processing means.
Claim 2
Dependent Claim
80 words
A digital signal processor (DSP) control apparatus comprising: an arithmetic processing means for performing digital signal arithmetic processing using a clock having a variable frequency; estimating means for estimating an arithmetic processing amount of said arithmetic processing means; calculation means for calculating a new clock frequency on the basis of an estimated arithmetic processing amount from said estimation means; and clock supply means for supplying a clock having a frequency calculated by said calculation means to said arithmetic processing means.
Claim 3
Dependent Claim
41 words
An apparatus according to claim 1 , wherein said estimation means estimates a new arithmetic processing amount of said arithmetic processing means on the basis of a transition of arithmetic processing amounts of said arithmetic processing means up to the present.
Claim 4
Dependent Claim
55 words
An apparatus according to claim 1 , wherein said estimation means adds/subtracts a predetermined arithmetic processing amount to/from an immediately preceding estimated arithmetic processing amount to estimate a new arithmetic processing amount of said arithmetic processing means on the basis of an increase/decrease of the immediately preceding arithmetic processing amount of said arithmetic processing means.
Claim 5
Dependent Claim
33 words
An apparatus according to claim 1 , wherein said estimation means estimates the arithmetic processing amount of said arithmetic processing means on the basis of operation information of a system using said DSP.
Claim 6
Dependent Claim
67 words
An apparatus according to claim 4 , wherein said apparatus further comprises a table that stores estimated arithmetic processing amounts of said arithmetic processing means in advance in correspondence with operating states of said system using said DSP, and said estimation means obtains an estimated arithmetic processing amount of said arithmetic processing means by looking up said table in accordance with an operating state of said system.
Claim 7
Dependent Claim
46 words
An apparatus according to claim 1 , wherein said estimation means estimates an arithmetic processing amount of said arithmetic processing means in accordance with a transition of a task cycle time when said arithmetic processing means performs multitask processing for a plurality of arithmetic processing operations.
Claim 8
Dependent Claim
46 words
An apparatus according to claim 1 , wherein said estimation means estimates an arithmetic processing amount of said arithmetic processing means on the basis of an arithmetic margin representing an occupation ratio of an idle state included in a processing operation of said arithmetic processing means.
Claim 9
Dependent Claim
52 words
An apparatus according to claim 1 , wherein said apparatus further comprises control means for controlling a CDMA (Code Division Multiple Access) radio terminal, and said arithmetic processing means performs a plurality of arithmetic processing operations associated with speech communication control in response to an arithmetic processing request from said control means.
Claim 10
Dependent Claim
69 words
A DSP (Digital Signal Processor) control method comprising the steps of: estimating an arithmetic processing amount of a DSP using a clock having a variable frequency where a required arithmetic process amount needed to process a plurality of currently running parallel tasks is unknown; calculating a new clock frequency on the basis of an estimating arithmetic processing amount; and supplying a clock having a calculated frequency to said DSP.
Claim 11
Dependent Claim
69 words
A DSP (Digital Signal Processor) control method comprising the steps of: estimating an arithmetic processing amount of a DSP using a clock having a variable frequency where a required arithmetic process amount needed to process a plurality of currently running parallel tasks is unknown; calculating a new clock frequency on the basis of an estimating arithmetic processing amount; and supplying a clock having a calculated frequency to said DSP.
Claim 12
Dependent Claim
43 words
A method according to claim 9 , wherein the estimating step comprises the step of estimating a new arithmetic processing amount of said DSP on the basis of a transition of arithmetic processing amounts of said DSP during a predetermined period of time.
Claim 13
Dependent Claim
63 words
A method according to claim 9 , wherein the estimating step comprises the steps of: determining an increase/decrease of an immediately preceding arithmetic processing amount of said DSP; and estimating a new arithmetic processing amount of said DSP by adding/subtracting a predetermined arithmetic processing amount to/from the immediate preceding estimated arithmetic processing amount of said DSP on the basis of a determination result.
Claim 14
Dependent Claim
35 words
A method according to claim 9 , wherein the estimating step comprises the step of estimating an arithmetic processing amount of said DSP on the basis of operation information of a system using said DSP.
Claim 15
Dependent Claim
61 words
A method according to claim 12 , wherein the estimating step comprises the steps of: storing in a table estimated arithmetic processing amounts of said DSP in correspondence with operating sates of said system using said DSP; and obtaining an estimated arithmetic processing amount of said DSP by looking up said table in accordance with an operating state of said system.
Claim 16
Dependent Claim
46 words
A method according to claim 9 , wherein the estimating step comprises the step of estimating an arithmetic processing amount of said DSP in accordance with a transition of a task cycle time when said DSP performs multitask processing for a plurality of arithmetic processing operations.
Claim 17
Dependent Claim
46 words
A method according to claim 9 , wherein the estimating step comprises the step of estimating an arithmetic processing amount of said DSP on the basis of an arithmetic margin representing an occupation ratio of an idle state included in a processing operation of said DSP.
Claim 18
Dependent Claim
38 words
A method according to claim 9 , wherein said DSP performs a plurality of arithmetic processing operations associated with speech communication control in response to an arithmetic processing request from a controller for controlling a CDMA radio terminal.
References Cited (Backward Citations)
JPS5647843A
Cited
GB2194082A
Cited
JPH01120610A
Cited
JPH0351902A
Cited
JPH03217916A
Cited
GB2246455A
Cited
JPH04235618A
Cited
JPH05113884A
Cited
JP3217916B2
Cited
JPH06232797A
Cited
JPH0746171A
Cited
GB2287555A
Cited
US5727193A
Cited
WO1995035540A1
Cited
US5996083A
Cited
JPH09114540A
Cited
US5815693A
Cited
JPH09297688A
Cited
US5774704A
Cited
JPH10187300A
Cited
JPH10313264A
Cited
US6049882A
Cited
US6141762A
Cited
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