Patent US2651939A successfully refreshed from Google Patents.
Patent US6514860B1 successfully refreshed from Google Patents.
US6514860B1
Expired / Lapsed
US
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Integration of organic fill for dual damascene process
Assignee: Semifab Ip Innovations LLC
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Filing: 2001-06-28
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Granted: 2003-02-04
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Expires: 2021-06-28
Abstract
Abstract A method of manufacturing a semiconductor device includes forming a second barrier layer over a first level, forming a first dielectric layer over the second barrier layer, forming a second dielectric layer over the first dielectric layer, etching the first and second dielectric layers to form an opening through the first dielectric layer and the second dielectric layer, depositing an organic fill material in the opening and removing a portion of the organic fill material before etching the second dielectric layer to form a trench. The organic fill material can then be completely removed and the second barrier layer is etched to expose the first level. The trench and a via are then filled with a conductive material to form a feature.
Inventors
- 👤 Lynne A. Okada
- 👤 Fei Wang
- 👤 James K. Kai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:15
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; H10W20/084; H10W20/085
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
139 words
A method of manufacturing a semiconductor device, comprising the steps of: forming a second barrier layer over a first level; forming a first dielectric layer over the second barrier layer; forming a second dielectric layer over the first dielectric layer; etching the first and second dielectric layers to form an opening through the first dielectric layer and the second dielectric layer, the opening including a via in the first dielectric layer; depositing an organic fill material in the opening; removing a portion of the organic fill material from the opening; etching the second dielectric layer to form a trench after the portion of the organic fill material is removed; completely removing the organic fill material; etching the second barrier layer to expose the first level; and filling the trench and the via with conductive material to form a feature.
Claim 2
Independent Claim
139 words
A method of manufacturing a semiconductor device, comprising the steps of: forming a second barrier layer over a first level; forming a first dielectric layer over the second barrier layer; forming a second dielectric layer over the first dielectric layer; etching the first and second dielectric layers to form an opening through the first dielectric layer and the second dielectric layer, the opening including a via in the first dielectric layer; depositing an organic fill material in the opening; removing a portion of the organic fill material from the opening; etching the second dielectric layer to form a trench after the portion of the organic fill material is removed; completely removing the organic fill material; etching the second barrier layer to expose the first level; and filling the trench and the via with conductive material to form a feature.
Claim 3
Dependent Claim
31 words
The method of manufacturing a semiconductor device according to claim 1 , wherein the portion of the organic fill material removed includes organic fill material positioned above the first dielectric layer.
Claim 4
Dependent Claim
36 words
The method of manufacturing a semiconductor device according to claim 1 , wherein at least 500 angstroms of the height of the organic fill material is removed during the partial removal of the organic fill material.
Claim 5
Dependent Claim
37 words
The method of manufacturing a semiconductor device according to claim 3 , wherein the at least 1000 angstroms of the height of the organic fill material is removed during the partial removal of the organic fill material.
Claim 6
Dependent Claim
21 words
The method of manufacturing a semiconductor device according to claim 1 , wherein the organic fill material is an anti-reflective material.
Claim 7
Dependent Claim
27 words
The method of manufacturing a semiconductor device according to claim 5 , wherein said step of removing the portion of the organic fill material is by oxidization.
Claim 8
Dependent Claim
26 words
The method of manufacturing a semiconductor device according to claim 1 , wherein said step of completely removing the organic fill material is by wet etching.
Claim 9
Dependent Claim
43 words
The method of manufacturing a semiconductor device according to claim 1 , further comprising the steps of: forming a first barrier layer between the first and second dielectric layers; and etching the first barrier layer after each etching of the second dielectric layer.
Claim 10
Dependent Claim
27 words
The method of manufacturing a semiconductor device according to claim 1 , wherein the conductive material and the first level comprise copper (Cu) or a Cu alloy.
Claim 11
Dependent Claim
44 words
The method of manufacturing a semiconductor device according to claim 1 , further comprising the steps of: forming a first resist over the second dielectric layer before etching to form the opening; and removing the first resist before the organic fill material is deposited.
Claim 12
Dependent Claim
47 words
The method of manufacturing a semiconductor device according to claim 10 , further comprising the steps of: forming a second resist over the second dielectric layer before etching to form the trench; and removing the second resist concurrently with the completely removal of the organic fill material.
Claim 13
Dependent Claim
24 words
The method of manufacturing a semiconductor device according to claim 1 , wherein the dielectric layer has a dielectric constant less than about 3.5.
Claim 14
Independent Claim
204 words
A method of manufacturing a semiconductor device, comprising the steps of: forming a second barrier layer over a first level; forming a first dielectric layer over the second barrier layer; forming a first barrier layer over the first dielectric layer forming a second dielectric layer over the first barrier layer; forming a first resist over the second dielectric layer; etching the first and second dielectric layers and the first barrier layer to form an opening through the first and dielectric layers and the first barrier layer, the opening including a via in the first dielectric layer; removing the first resist; depositing an organic fill material in the opening; removing a portion of the organic fill material above the first dielectric layer from the opening; depositing a second resist over the second dielectric layer, etching the second dielectric layer to form a trench after the portion of the organic fill material is removed; removing the second resist concurrently with the complete removal of the organic fill material after the trench is formed; etching the second barrier layer to expose the first level; and filling the trench and via with conductive material to form a feature; and planarizing a top surface of the second dielectric layer.
Claim 15
Independent Claim
204 words
A method of manufacturing a semiconductor device, comprising the steps of: forming a second barrier layer over a first level; forming a first dielectric layer over the second barrier layer; forming a first barrier layer over the first dielectric layer forming a second dielectric layer over the first barrier layer; forming a first resist over the second dielectric layer; etching the first and second dielectric layers and the first barrier layer to form an opening through the first and dielectric layers and the first barrier layer, the opening including a via in the first dielectric layer; removing the first resist; depositing an organic fill material in the opening; removing a portion of the organic fill material above the first dielectric layer from the opening; depositing a second resist over the second dielectric layer, etching the second dielectric layer to form a trench after the portion of the organic fill material is removed; removing the second resist concurrently with the complete removal of the organic fill material after the trench is formed; etching the second barrier layer to expose the first level; and filling the trench and via with conductive material to form a feature; and planarizing a top surface of the second dielectric layer.
Claim 16
Dependent Claim
31 words
The method of manufacturing a semiconductor device according to claim 13 , wherein the portion of the organic fill material removed includes organic fill material positioned above the first dielectric layer.
Claim 17
Dependent Claim
27 words
The method of manufacturing a semiconductor device according to claim 13 , wherein the conductive material and the first level comprise copper (Cu) or a Cu alloy.
Claim 18
Dependent Claim
24 words
The method of manufacturing a semiconductor device according to claim 13 , wherein the dielectric layer has a dielectric constant less than about 3.5.
Claim 19
Dependent Claim
21 words
The method of manufacturing a semiconductor device according to claim 13 , wherein the organic fill material is an anti-reflective material.
Claim 20
Dependent Claim
27 words
The method of manufacturing a semiconductor device according to claim 17 , wherein said step of removing the portion of the organic fill material is by oxidization.
Claim 21
Dependent Claim
36 words
The method of manufacturing a semiconductor device according to claim 13 , wherein at least 500 angstroms of the height of the organic fill material is removed during the partial removal of the organic fill material.
Claim 22
Dependent Claim
37 words
The method of manufacturing a semiconductor device according to claim 19 , wherein the at least 1000 angstroms of the height of the organic fill material is removed during the partial removal of the organic fill material.
References Cited (Backward Citations)
EP0895238A2
Cited
US6057239A
Cited
WO2000014793A2
Cited
US6251772B1
Cited
US6147404A
Cited
US6171949B1
Cited
US6391472B1
Cited
US6040243A
Cited
US6197681B1
Cited
US6323123B1
Cited
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