US6504408B1
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Method and apparatus to ensure DLL locking at minimum delay
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 2001-07-09
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Granted: 2003-01-07
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Expires: 2021-07-09
Abstract
Abstract A method and apparatus to ensure DLL locking at a minimum delay is provided. In one embodiment, a DLL circuit includes a phase detector, a counter, a programmable delay line, and a counter control circuit. Upon initialization of the DLL circuit, the counter control circuit is configured to cause the counter to count increment, regardless of the phase relationship between a reference clock signal and the output clock signal. The counter continues incrementing, thereby changing the phase relationship between the reference clock signal and the output clock signal by adjusting the delay of the programmable delay line. This eventually results in a phase lock between the reference clock signal and the output clock signal at a minimum delay. Once the DLL achieves a phase lock between the reference clock signal and the output clock signal, the counter increments or decrements its count in order to maintain or re-acquire a lock.
Inventors
- 👤 Vincent R. von Kaenel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:19
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/095; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
182 words
A delay locked loop (DLL) circuit comprising: a delay line configured to delay the transitions of a reference clock signal; a counter coupled to the delay line, wherein the counter provides a count to the delay line, wherein the amount of delay provided by the delay is determined by the count, a phase detector coupled to the delay line and a counter control circuit, wherein the phase detector is configured to receive an output clock signal from the delay line and the reference clock signal, and wherein the phase detector is configured to produce one or more output signals dependent upon the phase relationship between the reference clock signal and the output clock signal; and the counter control circuit coupled to receive the one or more output signals from the phase detector, wherein the counter control circuit is configured, responsive to a reset of the DLL circuit, to cause the counter to count in a predetermined direction even in an event that the one or more output signals of the phase detector indicate counting in an opposite direction to the predetermined direction.
Claim 2
Dependent Claim
182 words
A delay locked loop (DLL) circuit comprising: a delay line configured to delay the transitions of a reference clock signal; a counter coupled to the delay line, wherein the counter provides a count to the delay line, wherein the amount of delay provided by the delay is determined by the count, a phase detector coupled to the delay line and a counter control circuit, wherein the phase detector is configured to receive an output clock signal from the delay line and the reference clock signal, and wherein the phase detector is configured to produce one or more output signals dependent upon the phase relationship between the reference clock signal and the output clock signal; and the counter control circuit coupled to receive the one or more output signals from the phase detector, wherein the counter control circuit is configured, responsive to a reset of the DLL circuit, to cause the counter to count in a predetermined direction even in an event that the one or more output signals of the phase detector indicate counting in an opposite direction to the predetermined direction.
Claim 3
Dependent Claim
38 words
The DLL as recited in claim 1 wherein causing the counter to count in a predetermined direction comprises causing the counter to increment, even in an event that the one or more output signals do not indicate increment.
Claim 4
Dependent Claim
36 words
The DLL as recited in claim 2 wherein the counter control circuit is configured to cause the counter to count in a predetermined direction until detecting a predetermined condition of the one or more output signals.
Claim 5
Dependent Claim
32 words
The DLL as recited in claim 3 wherein the predetermined condition of the one or more output signals includes the one or more output signals transitioning from indicating increment to indicating decrement.
Claim 6
Dependent Claim
55 words
The DLL circuit as recited in claim 4 , wherein the counter control circuit is further configured to generate a first signal that causes the counter to increment and a second signal which causes the counter to decrement, and wherein the first signal is activated responsive to the reset and remains active until said transition.
Claim 7
Dependent Claim
33 words
The DLL circuit as recited in claim 1 , wherein the DLL circuit is configured to lock at N=1, wherein N is an integer multiple of the period of the reference clock signal.
Claim 8
Dependent Claim
24 words
The DLL circuit as recited in claim 1 , wherein the phase detector and the delay line each include one or more delay elements.
Claim 9
Dependent Claim
23 words
The DLL circuit as recited in claim 1 , wherein the counter is configured to reset to zero responsive to the reset signal.
Claim 10
Dependent Claim
59 words
The DLL circuit as recited in claim 1 , wherein the one or more output signals produced by the phase detector include an UP signal and a LOCK signal, wherein the UP signal, when active, indicates that the counter is to increment, and wherein the LOCK signal, when active indicates that the DLL circuit has achieved a phase lock.
Claim 11
Independent Claim
89 words
A method of operating a delay locked loop circuit (DLL) circuit, the method comprising: generating one or more output signals from a phase detector, the one or more output signals indicative of a phase relationship between a reference clock signal and an output clock signal; and controlling a counter to count in a predetermined direction in response to a reset of the DLL circuit even in an event that the one or more output signals of the phase detector indicate counting in an opposite direction to the predetermined direction.
Claim 12
Independent Claim
89 words
A method of operating a delay locked loop circuit (DLL) circuit, the method comprising: generating one or more output signals from a phase detector, the one or more output signals indicative of a phase relationship between a reference clock signal and an output clock signal; and controlling a counter to count in a predetermined direction in response to a reset of the DLL circuit even in an event that the one or more output signals of the phase detector indicate counting in an opposite direction to the predetermined direction.
Claim 13
Dependent Claim
31 words
The method as recited in claim 10 wherein the controlling comprises causing the counter to increment, even in an event that the one or more output signals do not indicate increment.
Claim 14
Dependent Claim
23 words
The method as recited in claim 11 wherein the controlling continues until detecting a predetermined condition of the one or more output signals.
Claim 15
Dependent Claim
27 words
The method as recited in claim 12 wherein the detecting comprises detecting a transition of the one or more output signals from indicating increment to indicating decrement.
Claim 16
Dependent Claim
49 words
The method as recited in claim 13 , wherein the controlling comprises generating a first signal that causes the counter to increment and a second signal which causes the counter to decrement, and wherein the first signal is activated responsive to the reset and remains active until said transition.
Claim 17
Dependent Claim
19 words
The method as recited in claim 10 further comprising initializing the counter to zero in response to the reset.
Claim 18
Dependent Claim
58 words
The method as recited in claim 10 , wherein the one or more output signals produced by the phase detector include an UP signal and a LOCK signal, wherein the UP signal, when active, indicates that the counter is to increment, and wherein the LOCK signal, when active indicates that the DLL circuit has achieved a phase lock.
Claim 19
Dependent Claim
184 words
A carrier medium comprising one or more databases representing: a delay line configured to delay the transitions of a reference clock signal; a counter coupled to the delay line, wherein the counter provides a count to the delay line, wherein the amount of delay provided by the delay is determined by the count, a phase detector coupled to the delay line and a counter control circuit, wherein the phase detector is configured to receive an output clock signal from the delay line and the reference clock signal, and wherein the phase detector is configured to produce one or more output signals dependent upon the phase relationship between the reference clock signal and the output clock signal; and the counter control circuit coupled to receive the one or more output signals from the phase detector, wherein the counter control circuit is configured, responsive to a reset of the DLL circuit, to cause the counter to count in a predetermined direction even in an event that the one or more output signals of the phase detector indicate counting in an opposite direction to the predetermined direction.
Claim 20
Dependent Claim
184 words
A carrier medium comprising one or more databases representing: a delay line configured to delay the transitions of a reference clock signal; a counter coupled to the delay line, wherein the counter provides a count to the delay line, wherein the amount of delay provided by the delay is determined by the count, a phase detector coupled to the delay line and a counter control circuit, wherein the phase detector is configured to receive an output clock signal from the delay line and the reference clock signal, and wherein the phase detector is configured to produce one or more output signals dependent upon the phase relationship between the reference clock signal and the output clock signal; and the counter control circuit coupled to receive the one or more output signals from the phase detector, wherein the counter control circuit is configured, responsive to a reset of the DLL circuit, to cause the counter to count in a predetermined direction even in an event that the one or more output signals of the phase detector indicate counting in an opposite direction to the predetermined direction.
Claim 21
Dependent Claim
40 words
The carrier medium as recited in claim 17 , wherein causing the counter to count in a predetermined direction comprises causing the counter to increment, even in an event that the one or more output signals do not indicate increment.
Claim 22
Dependent Claim
38 words
The carrier medium as recited in claim 18 , wherein the counter control circuit is configured to cause the counter to count in a predetermined direction until detecting a predetermined condition of the one or more output signals.
Claim 23
Dependent Claim
34 words
The carrier medium as recited in claim 19 , wherein the predetermined condition of the one or more output signals includes the one or more output signals transitioning from indicating increment to indicating decrement.
Claim 24
Dependent Claim
55 words
The carrier medium as recited in claim 20 , wherein the counter control circuit is further configured to generate a first signal that causes the counter to increment and a second signal which causes the counter to decrement, and wherein the first signal is activated responsive to the reset and remains active until said transition.
References Cited (Backward Citations)
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| 3.5 Years (Year 4) | 2006-01-06 | 2006-07-08 | 2007-01-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2010-01-06 | 2010-07-08 | 2011-01-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2014-01-06 | 2014-07-08 | 2015-01-07 | $7700.00 | Window Closed / Lapsed |