Circuit for eliminating off-chip to on-chip clock skew

Claim 2

A circuit on an integrated circuit for eliminating clock skew between an off-chip clock signal originating off the integrated circuit and an on-chip clock signal produced on the integrated circuit, the circuit comprising: phase delay means for receiving the off-chip clock signal and phase delaying the off-chip-clock signal an amount to produce the on-chip clock signal, the phase delay means including a first delay path for phase delaying the off-chip clock signal the amount of phase delay, phase delay through the first delay path being adjustable, a second delay path for phase delaying the off-chip clock signal the amount of phase delay, phase delay through the second delay path being adjustable, the off-chip clock signal being phased delayed an identical amount at an output of the first delay path as at an output of the second delay path, except when phase delay through the first delay path or through the second delay path is being adjusted, and selection means, coupled to the first delay path and the second delay path for selecting one of the first delay path and the second delay path to produce the on-chip clock signal; and, phase detector means, coupled to the phase delay means, for receiving the off-chip clock signal and the on-chip clock signal and generating control signals which indicate, based on phase difference between the off-chip clock signal and the on-chip clock signal, whether and how to adjust the amount of phase delay by which the first delay path and the second delay path delays the off-chip clock signal to produce the on-chip clock signal; wherein when phase delay through the first delay path is adjusted, the selection means selects the second delay path and when phase delay through the second delay path is adjusted the selection means selects the first delay path.

Claim 3

A circuit as in claim 1 wherein the phase delay means additionally comprises: counter means, coupled to the first delay path and the second delay path, for generating a phase delay value, the phase delay value determining the phase delay through the first delay path and the second delay path; and, control means coupled to the phase detector means and the counter means for causing the counter means to increment and decrement the phase delay value based on the control signals.

Claim 4

A circuit as in claim 2 wherein the first delay path includes a plurality of individual phase delay elements, phase delay through each phase delay element based on the phase delay value.

Claim 5

A circuit as in claim 2 wherein, the phase detector means includes a first flip-flop means for receiving the off-chip clock signal on an FF input, for being clocked by the on-chip clock signal and for producing a first control signal; and, a second flip-flop means for receiving the off-chip clock signal on an FF input, for being clocked by the on-chip clock signal after the on-chip clock signal is slightly phase delayed and for producing a second control signal

Claim 6

A circuit as in claim 4 wherein the phase detector means additionally includes filter means, coupled to the first flip-flop and the second flip-flop, for filtering the first control signal and the second control signal to eliminate effects of noise within the on-chip clock signal and the off-chip clock signal.

Claim 9

A method as in claim 6 wherein step (a) additionally comprises the substeps of: (a.4) generating a phase delay value, the phase delay value determining the phase delay through the first delay path and the second delay path; and, (a.5) incrementing and decrementing the phase delay value based on the control signals.

Claim 10

A method as in claim 7 wherein substep (a.1) includes using a first plurality of phase delay elements connected in series to delay the off-chip clock signal, phase delay through each phase delay element being based on the phase delay value and wherein substep (a.2)includes using a second plurality of phase delay elements connected in series to delay the off-chip clock signal, phase delay through each phase delay element being based on the phase delay value.

Claim 11

A method as in claim 6 wherein step (b) comprises the substeps of: (b.1) producing a first control signal by a first flip-flop, including the substeps of receiving, by the first flip-flop, the off-chip clock signal on an FF input, and clocking the first flip-flop by the on-chip clock signal to produce the first control signal; (b.2) slightly delaying the phase of the on-chip clock signal; and, (b.3) producing a second control signal by a second flip-flop, including the substeps of receiving, by the second flip-flop, the off-chip clock signal on an FF input, and clocking the second flip-flop, by the on-chip clock signal after the on-chip clock signal is slightly phase delayed in substep (b.2), to produce the second control signal.

Claim 12

A method as in claim 9 wherein step (b) additionally includes the substep of filtering the first control signal and the second control signal to eliminate effects of noise within the on-chip clock signal and the off-chip clock signal.

Claim 13

A circuit on an integrated circuit for eliminating clock skew between an off-chip clock signal originating off the integrated circuit and an on-chip clock signal produced on the integrated circuit, the circuit comprising: phase delay means for receiving the off-chip clock signal and phase delaying the off-chip clock signal an amount to produce the on-chip clock signal, the phase delay means including a first delay path for phase delaying the off-chip clock signal the amount of phase delay, phase delay through the first delay path being adjustable, counter means, coupled to the phase delay means, for generating a phase delay value, the phase delay value determining the phase delay through the first delay path, wherein the counter means generates the phase delay value on a plurality of digit outputs, each digit output representing an order of magnitude of delay, and control means coupled to the phase delay means and the counter means for causing the counter means to increment and decrement the phase delay value based on the control signals; a second delay path for delaying the off-chip clock signal the amount of phase delay, phase delay through the second delay path being adjustable, the off-chip clock signal being phased delayed an identical amount at an output of the first delay path as at an output of the second delay path, except when phase delay through the first delay path or through the second delay path is being adjusted, and selection means, coupled to the first delay path and the second delay path, for selecting one of the first delay path and the second delay path to produce the on-chip clock signal; and, phase detector means, coupled to the phase delay means, for receiving the off-chip clock signal and the on-chip clock signal and generating control signals which indicate, based on phase difference between the off-chip clock signal and the on-chip clock signal, whether and how to adjust the amount of phase delay by which the phase delay means delays the off-chip clock signal to produce the on-chip clock signal; wherein when phase delay through the first delay path is adjusted, the selection means selects the second delay path and when phase delay through the second delay path is adjusted the selection means selects the first delay path.

Claim 14

A circuit on an integrated circuit for eliminating clock skew between an off-chip clock signal originating off the integrated circuit and an on-chip clock signal produced on the integrated circuit, the circuit comprising: phase delay means for receiving the off-chip clock signal and phase delaying the off-chip clock signal an amount to produce the on-chip clock signal, the phase delay means including a first delay path for phase delaying the off-chip clock signal the amount of phase delay, phase delay through the first delay path being adjustable, counter means, coupled to the phase delay means, for generating a phase delay value, the phase delay value determining the phase delay through the first delay path, wherein the counter means generates the phase delay value on a plurality of digit outputs, each digit output representing an order of magnitude of delay, and control means coupled to the phase delay means and the counter means for causing the counter means to increment and decrement the phase delay value based on the control signals; a second delay path for delaying the off-chip clock signal the amount of phase delay, phase delay through the second delay path being adjustable, the off-chip clock signal being phased delayed an identical amount at an output of the first delay path as at an output of the second delay path, except when phase delay through the first delay path or through the second delay path is being adjusted, and selection means, coupled to the first delay path and the second delay path, for selecting one of the first delay path and the second delay path to produce the on-chip clock signal; and, phase detector means, coupled to the phase delay means, for receiving the off-chip clock signal and the on-chip clock signal and generating control signals which indicate, based on phase difference between the off-chip clock signal and the on-chip clock signal, whether and how to adjust the amount of phase delay by which the phase delay means delays the off-chip clock signal to produce the on-chip clock signal; wherein when phase delay through the first delay path is adjusted, the selection means selects the second delay path and when phase delay through the second delay path is adjusted the selection means selects the first delay path.

Claim 15

A circuit as in claim 11 wherein the first delay path includes a plurality of individual phase delay elements connected in series, each individual phase delay element in the plurality of individual phase delay elements connected to a digit output of the counter means, an amount of delay through each individual phase delay element dependent upon a signal value on the digit output to which the individual phase delay element is connected so that when the signal value on the digit output is a first value there is no phase delay through the individual phase delay element and when the signal value on the digit output is a second value there is a phase delay through the individual phase delay element which corresponds to the order of magnitude of delay represented by the digit output to which the individual phase delay element is connected.

Claim 18

A method as in claim 13 wherein substep (a.1) includes using a first plurality of phase delay elements connected in series to delay the off-chip clock signal, each individual phase delay element in the plurality of individual phase delay elements connected to a digit output of the counter means, an amount of delay through each individual phase delay element dependent upon a signal value on the digit output to which the individual phase delay element is connected so that when the signal value on the digit output is a first value there is no phase delay through the individual phase delay element and when the signal value on the digit output is a second value there is a phase delay through the individual phase delay element which corresponds to the order of magnitude of delay represented by the digit output to which the individual phase delay element is connected.