US5180937A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Delay compensator and monitor circuit having timing generator and sequencer
Assignee: LSI Corp
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Filing: 1992-02-28
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Granted: 1993-01-19
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Expires: 2012-02-28
Abstract
Abstract A delay compensator circuit is disclosed to compensate for variations in temperature, supply voltage and process. A monitor circuit is further disclosed that allows the monitoring of the delay of a delay element. The delay compensator circuit and monitor circuit lend themselves easily to the ASIC design methodology since they use conventional ASIC building blocks; namely gates, memory elements and delay elements. The delay compensator and monitor use a time base to track variations in circuit parameters by monitoring the delay through a delay element (delay line or sub-circuit). Compensation may be achieved by switching delays in or out of the circuit to be compensated based on variations of temperature, voltage, and process as measured using the time base. The delay compensator permits the designer to control the output hold time independently of the output delay time. The delay compensator enables a latching device to hold the output signal for the required duration after a reference.
Inventors
- 👤 Douglas Laird
- 👤 Godfrey P. D'Souza
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 19:57
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/133; H03K2005/00013; H03K2005/00078; H03K2005/00097; H03K2005/00123; H03K2005/0013; H03K2005/00143
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
162 words
A delay compensator circuit connectable to a signal path of a circuit to be compensated, said delay compensator circuit comprising: at least one test delay element having an input terminal and an output terminal; a timing generator and sequencer circuit coupled to said test delay element, said timing generator and sequencer circuit providing a test signal to the input terminal of said test delay element and monitoring the output terminal of said test delay element at a given time after said test signal is provided to said input terminal of said test delay element, wherein said timing generator and sequencer circuit generates a delay select signal indicative of a voltage level at said output terminal of said test delay element at the given time; at least one signal path delay element selectively connectable into the signal path of the circuit to be compensated; and means for switching said signal path delay element into said signal path depending upon said delay select signal.
Claim 2
Dependent Claim
162 words
A delay compensator circuit connectable to a signal path of a circuit to be compensated, said delay compensator circuit comprising: at least one test delay element having an input terminal and an output terminal; a timing generator and sequencer circuit coupled to said test delay element, said timing generator and sequencer circuit providing a test signal to the input terminal of said test delay element and monitoring the output terminal of said test delay element at a given time after said test signal is provided to said input terminal of said test delay element, wherein said timing generator and sequencer circuit generates a delay select signal indicative of a voltage level at said output terminal of said test delay element at the given time; at least one signal path delay element selectively connectable into the signal path of the circuit to be compensated; and means for switching said signal path delay element into said signal path depending upon said delay select signal.
Claim 3
Dependent Claim
34 words
The delay compensator circuit as recited in claim 1 comprising additional signal path delay elements each selectively connectable into the signal path of the circuit to be compensated depending upon said delay select signal.
Claim 4
Dependent Claim
95 words
The delay compensator circuit as recited in claim 2 further comprising additional test delay elements each having an input terminal and an output terminal coupled to said timing generator and sequencer circuit, wherein said timing generator and sequencer circuit provides the test signal to each of said additional test delay elements and monitors the voltage level at the output terminals of each additional test delay element at the given time, and generates separate delay select signals each indicative of the voltage level at the output terminals of each test delay element at the given time.
Claim 5
Dependent Claim
37 words
The delay compensator circuit as recited in claim 1 wherein said timing generator and sequencer circuit comprises a first and a second flip-flop connected to receive an externally generated clock signal and for generating said test signal.
Claim 6
Dependent Claim
18 words
The delay compensator circuit as recited in claim 1 wherein said test delay element is a delay line.
Claim 7
Dependent Claim
26 words
The delay compensator circuit as recited in claim 1 wherein said means for switching said signal path delay element into said signal path includes a multiplexer.
Claim 8
Dependent Claim
121 words
A delay monitor circuit for monitoring the delay of a test delay element having an input terminal and an output terminal, said delay monitor circuit comprising a timing generator and sequencer circuit coupled to said test delay element, said timing generator and sequencer circuit providing a test signal to the input terminal of said test delay element and monitoring a voltage level at the output terminal of said test delay element at a given time after said test signal is provided to said input terminal of said test delay element, wherein said timing generator and sequencer circuit generates a delay monitor output signal indicative of the voltage level at said output terminal of said test delay element at the given time.
Claim 9
Dependent Claim
121 words
A delay monitor circuit for monitoring the delay of a test delay element having an input terminal and an output terminal, said delay monitor circuit comprising a timing generator and sequencer circuit coupled to said test delay element, said timing generator and sequencer circuit providing a test signal to the input terminal of said test delay element and monitoring a voltage level at the output terminal of said test delay element at a given time after said test signal is provided to said input terminal of said test delay element, wherein said timing generator and sequencer circuit generates a delay monitor output signal indicative of the voltage level at said output terminal of said test delay element at the given time.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-01-19 | 1996-07-20 | 1997-01-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-01-19 | 2000-07-20 | 2001-01-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-01-19 | 2004-07-20 | 2005-01-19 | $7700.00 | Window Closed / Lapsed |