Variable self-correcting digital delay circuit

Claim 2

A monolithic integrated variable self-correcting delay circuit having a plurality of components thereon for producing an output signal, the time of occurrence of which is delayed by precise amounts with respect to an input signal applied thereto, wherein a user determines the amount of delay that is desirable to introduce, comprising: oscillator means to generate signals having a frequency of oscillation; first counter means coupled to said oscillator means to convert said frequency of oscillation into a first number of pulses; circuit means for receiving a data input signal indicative of the desired delay determined by the user and for converting said input signal into a second number of pulses; comparator means connected to said first counter means and to said circuit means to compare said first number of pulses to said second number of pulses; second counter means responsive to said comparator means and driving said oscillator means for providing a signal that modifies the frequency of oscillation of said oscillator means; and delay means responsive to said circuit means and to said second counter means for providing the desired delay introduced by the user.

Claim 3

The monolithic integrated variable self-correcting delay circuit as in claim 1 is further characterized by being comprised of only digital components.

Claim 4

The monolithic integrated variable self-correcting delay circuit as in claim 1 is further characterized by having said first number of pulses of said first counter means vary as a function of delay caused by technology, process, temperature and power supply variations.

Claim 5

The monolithic integrated variable self-correcting delay circuit as in claim 1, wherein said first counter means counts said first number of pulses in accordance with the following relationship: Number of pulses=amount of delay/first counter means period, wherein said amount of delay corresponds to said desired delay.

Claim 6

The monolithic integrated variable self-correcting delay circuit as in claim 4, wherein said second number of pulses is inputted into said comparator means for comparison with said first number of pulses to determine the amount of correction to the frequency of said oscillator means.

Claim 7

The monolithic integrated variable self-correcting delay circuit as in claim 5, wherein said second counter means comprises an up/down counter, the content of which is incremented or decremented in accordance with the outcome of said comparison in said comparator means, and wherein said first number of pulses is, respectively, above or below said second number of pulses.

Claim 8

The monolithic integrated variable self-correcting delay circuit as in claim 1, wherein said first counter means comprises a loop counter to reflect contemporaneously changes in said frequency of oscillation caused by advancing or retarding the output signal with respect to the input signal in accordance with said delay means.

Claim 9

The monolithic integrated variable self-correcting delay circuit as in claim 1, wherein the delay provided by said delay means between an output and an input signals is determined by a coarse delay and by a fine delay circuit means, the input of said coarse delay means is attached to an input terminal and the output of said fine delay is attached to an output terminal, and wherein said coarse delay is responsive to the amount of delay determined by the user, the said fine delay is controlled by said second counter means.

Claim 10

A monolithic integrated variable self-correcting delay circuit having a plurality of components thereon for producing an output signal, the time of occurrence of which is delayed by precise amounts with respect to an input signal applied thereto, wherein the user determines the amount of delay that is desirable to introduce, comprising: recirculating-loop-frequency oscillator means for generating signals having a frequency of oscillation determined by the monolithic integrated variable self-correcting delay circuit; first counter means responsive to said recirculating-loop-frequency oscillator means having a plurality of outputs for converting said frequency of oscillation into a first number of pulses; select circuit means having at least two inputs and one output, the first of said at least two inputs is connected to an oscillator, and the second to a delay enable signal, said select circuit means setting the monolithic integrated variable self-correcting delay circuit in a delay mode; controller circuit means responsive to said select circuit means for defining a time window during which said first pulses are counted; data scan-in circuit means for receiving a data signal indicative of the desired delay determined by the user and for converting said input signal into a second number of pulses, said data scan-in circuit means having at least two inputs and a plurality of outputs, the first of said two inputs is connected to a clock and the second input for receiving said data signals; comparator means responsive to said data scan-in circuit means and to said first counter means to compare said first number of pulses to said second number of pulses second counter means responsive to said comparator means and driving said recirculating-loop-frequency oscillator means for providing a signal to vary the delay indicated by the data scan-in circuit means, thereby modifying the frequency of oscillation of said recirculating-loop-frequency oscillator means; and timing adjustment means coupled to said first and second counter means for advancing or retarding the output signal with respect to the input signal in accordance with the lapse of time defined by the outcome of the comparison of said first number of pulses to said second number of pulses.

Claim 11

A monolithic integrated variable self-correcting delay circuit having a plurality of components thereon for producing an output signal, the time of occurrence of which is delayed by precise amounts with respect to an input signal applied thereto, wherein the user determines the amount of delay that is desirable to introduce, comprising: recirculating-loop-frequency oscillator means for generating signals having a frequency of oscillation determined by the monolithic integrated variable self-correcting delay circuit; first counter means responsive to said recirculating-loop-frequency oscillator means having a plurality of outputs for converting said frequency of oscillation into a first number of pulses; select circuit means having at least two inputs and one output, the first of said at least two inputs is connected to an oscillator, and the second to a delay enable signal, said select circuit means setting the monolithic integrated variable self-correcting delay circuit in a delay mode; controller circuit means responsive to said select circuit means for defining a time window during which said first pulses are counted; data scan-in circuit means for receiving a data signal indicative of the desired delay determined by the user and for converting said input signal into a second number of pulses, said data scan-in circuit means having at least two inputs and a plurality of outputs, the first of said two inputs is connected to a clock and the second input for receiving said data signals; comparator means responsive to said data scan-in circuit means and to said first counter means to compare said first number of pulses to said second number of pulses second counter means responsive to said comparator means and driving said recirculating-loop-frequency oscillator means for providing a signal to vary the delay indicated by the data scan-in circuit means, thereby modifying the frequency of oscillation of said recirculating-loop-frequency oscillator means; and timing adjustment means coupled to said first and second counter means for advancing or retarding the output signal with respect to the input signal in accordance with the lapse of time defined by the outcome of the comparison of said first number of pulses to said second number of pulses.

Claim 12

The monolithic integrated variable self-correcting delay circuit as in claim 9, wherein said first number of pulses are counted within said time window set by said controller circuit means and wherein said second number of pulses is determined by said data scan-in circuit means.

Claim 13

The monolithic integrated variable self-correcting delay circuit as in claim 9, wherein said first counter means counts said first number of pulses in accordance with the following relationship: Number of pulses=amount of delay/first counter means period, wherein said amount of delay corresponds to said desired delay.

Claim 14

The monolithic integrated variable self-correcting delay circuit as in claim 9, wherein said first counter means is connected to the output of a select circuit means which inputs are coupled to the output of said recirculating-loop-frequency means and to outputs of said controller circuit means.