Patent US6501311B2 successfully refreshed from Google Patents.
US6501311B2
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System and method for compensating for supply voltage induced signal delay mismatches
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 2001-01-24
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Granted: 2002-12-31
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Expires: 2021-01-24
Abstract
Abstract Various systems and methods providing signal delay compensation for circuits such as a multi-pair gigabit Ethernet transceiver are disclosed. In an analog implementation a buffer with an adjustable delay may be used to minimize the delay mismatch between clock trees. The delay of the adjustable-delay buffer is controlled by bias voltages that determine the charging and discharging current to the adjustable buffer. A phase detector circuit is used to compare the clock phases for rising and falling edges, and to adjust the bias voltages that control these edges. In a digital implementation a selector switch, responsive to a phase detector, may be used to route clock signals through circuit elements to delay clock signals.
Inventors
- 👤 Christian A. J. Lutkemeyer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:52
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; G06F3/00; G06F3/002; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/085; H03L7/087
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
139 words
A system for compensating for phase differences between a plurality of signals, comprising: a level adjuster for modifying a signal level of a signal to generate a first signal associated with a first signal level that is different than a second signal level associated with a second signal; at least one phase comparator for comparing a phase of the first signal with a phase of the second signal, and for generating at least one compensation signal indicative of a phase difference between the first signal and the second signal; and at least one delay adjuster coupled to the at least one phase comparator and responsive to the at least one compensation signal, for delaying at least one of the first signal and the second signal to compensate for the phase difference between the first signal and the second signal.
Claim 2
Independent Claim
139 words
A system for compensating for phase differences between a plurality of signals, comprising: a level adjuster for modifying a signal level of a signal to generate a first signal associated with a first signal level that is different than a second signal level associated with a second signal; at least one phase comparator for comparing a phase of the first signal with a phase of the second signal, and for generating at least one compensation signal indicative of a phase difference between the first signal and the second signal; and at least one delay adjuster coupled to the at least one phase comparator and responsive to the at least one compensation signal, for delaying at least one of the first signal and the second signal to compensate for the phase difference between the first signal and the second signal.
Claim 3
Dependent Claim
19 words
The system of claim 1 wherein the at least one delay adjuster comprises at least one adjustable delay buffer.
Claim 4
Dependent Claim
118 words
The system of claim 2 wherein the at least one phase comparator comprises: a rising edge phase comparator for comparing a rising edge of the first signal with a rising edge of the second signal, for generating at least one rising edge compensation signal indicative of a phase difference between the rising edge of the first signal and the rising edge of the second signal; and a falling edge phase comparator for comparing a falling edge of the first signal with a falling edge of the second signal, for generating at least one falling edge compensation signal indicative of a phase difference between the falling edge of the first signal and the falling edge of the second signal.
Claim 5
Dependent Claim
63 words
The system of claim 3 wherein the at least one adjustable delay buffer comprises: delays the rising edge of at least one of the first signal and the second signal in response to the rising edge compensation signal; and delays the falling edge of at least one of the first signal and the second signal in response to the falling edge compensation signal.
Claim 6
Dependent Claim
63 words
The system of claim 2 wherein the at least one adjustable delay buffer comprises: at least one buffer transistor for buffering the first signal; and at least one control transistor, responsive to the at least one compensation signal, for adjusting current flow through the at least one buffer transistor for controlling delay of the first signal through the at least one buffer transistor.
Claim 7
Dependent Claim
143 words
An integrated circuit including circuitry for compensating for phase differences between a plurality of clock signals, comprising: a level adjuster for modifying a signal level of a signal to generate a first signal associated with a first signal level that is different than a second signal level associated with a second signal; at least one phase comparator for comparing a phase of the first signal with a phase of the second signal, and for generating at least one compensation signal indicative of a phase difference between the first signal and the second signal; and at least one delay adjuster coupled to the at least one phase comparator and responsive to the at least one compensation signal, for delaying at least one of the first signal and the second signal to compensate for the phase difference between the first signal and the second signal.
Claim 8
Dependent Claim
143 words
An integrated circuit including circuitry for compensating for phase differences between a plurality of clock signals, comprising: a level adjuster for modifying a signal level of a signal to generate a first signal associated with a first signal level that is different than a second signal level associated with a second signal; at least one phase comparator for comparing a phase of the first signal with a phase of the second signal, and for generating at least one compensation signal indicative of a phase difference between the first signal and the second signal; and at least one delay adjuster coupled to the at least one phase comparator and responsive to the at least one compensation signal, for delaying at least one of the first signal and the second signal to compensate for the phase difference between the first signal and the second signal.
Claim 9
Dependent Claim
15 words
The integrated circuit of claim 6 wherein the integrated circuit comprises a gigabit ethernet transceiver.
Claim 10
Dependent Claim
36 words
The integrated circuit of claim 7 wherein the first signal comprises a clock signal that is associated with at least one of a near end crosstalk canceller, an echo canceller and a decision feed back equalizer.
Claim 11
Independent Claim
96 words
A method for compensating for phase differences between a plurality of signals associated with a plurality of signal levels, comprising the steps of: generating a first signal associated with a first signal level; generating a second signal associated with a second signal level; comparing a phase of the first signal with a phase of the second signal to generate at least one compensation signal indicative of a phase difference between the first signal and the second signal; and delaying the first signal to compensate for the phase difference between the first signal and the second signal.
Claim 12
Independent Claim
96 words
A method for compensating for phase differences between a plurality of signals associated with a plurality of signal levels, comprising the steps of: generating a first signal associated with a first signal level; generating a second signal associated with a second signal level; comparing a phase of the first signal with a phase of the second signal to generate at least one compensation signal indicative of a phase difference between the first signal and the second signal; and delaying the first signal to compensate for the phase difference between the first signal and the second signal.
Claim 13
Dependent Claim
145 words
The method of claim 9 wherein: the comparing step further comprises the steps of: comparing a rising edge of the first signal with a rising edge of the second signal to generate a rising edge compensation signal indicative of a phase difference between the rising edge of the first signal and the rising edge of the second signal; and comparing a falling edge of the first signal with a falling edge of the second signal to generate a falling edge compensation signal indicative of a phase difference between the falling edge of the first signal and the falling edge of the second signal; and the delaying step further comprises the steps of: delaying the rising edge of the first signal in response to the rising edge compensation signal; and delaying the falling edge of the first signal in response to the falling edge compensation signal.
Claim 14
Dependent Claim
39 words
The method of claim 9 further comprising the step of selectively routing the first signal through at least one of a plurality of delay elements to compensate for the phase difference between the first signal and the second signal.
Claim 15
Dependent Claim
24 words
The method of claim 9 further comprising the steps of generating the first signal and the second signal with a plurality of clock trees.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-12-30 | 2006-07-01 | 2006-12-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-12-30 | 2010-07-01 | 2010-12-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-12-30 | 2014-07-01 | 2014-12-31 | $7700.00 | Window Closed / Lapsed |