Clock synchronizing circuit

Claim 2

A clock synchronizing circuit, comprising: a phase comparator circuit that outputs a first phase error detecting signal based on a time-delayed external clock signal and a feedback clock signal, and a second phase error detecting signal based on a first external clock signal and a time-delayed feedback clock signal; a phase compensator circuit that inputs the first external clock signal and outputs a second external clock signal, wherein the phase compensator circuit has a first mode of operation, in which the phase compensator circuit phase-compensates the first external clock signal to generate the second external clock signal, and a second mode of operation, in which the phase compensator does not phase-compensate the first external clock signal, wherein the first and second operating modes are selectable based on the first and second phase error detecting signals; and a charge pump that generates a charge and adjusts a magnitude of the charge in response to the first and second phase error detecting signals.

Claim 3

The clock synchronizing circuit of claim 1 , wherein the phase comparator circuit comprises: a first phase comparator that determines a first phase difference between the time-delayed external clock signal and the feedback clock signal, and outputs the first phase error detecting signal; and a second phase comparator that determines a second phase difference between the external clock signal and the time-delayed feedback clock signal, and outputs the second phase error detecting signal.

Claim 4

A clock synchronizing circuit as claimed in claim 1 , wherein the phase compensator inputs the charge generated by the charge pump and, when the phase compensator is in the first mode of operation, compensates the phase of the first external clock signal in accordance with the magnitude of the charge from the charge pump.

Claim 5

A clock synchronizing circuit, comprising: a first phase comparator that receives a time-delayed external clock signal and a feedback clock signal, determines a first phase difference between the time-delayed external clock signal and the feedback clock signal, and outputs a first phase error detecting signal; a second phase comparator that receives a first external clock signal and a time-delayed feedback clock signal, determines a second phase difference between the first external clock signal and the time-delayed feedback clock signal, and outputs a second phase error detecting signal; a phase compensator that inputs the first external clock signal and outputs a second external clock signal, wherein the phase compensator has a first mode of operation, in which the phase compensator phase-compensates the first external clock signal to generate the second external clock signal, and a second mode of operation, in which the phase compensator does not phase-compensate the first external clock signal, wherein the first and second modes are selectable based on the first and second phase error detecting signals; and a charge pump that generates a charge and adjusts a magnitude of the charge in response to the first and second phase error detecting signals.

Claim 6

A clock synchronizing circuit, comprising: a first phase comparator that receives a time-delayed external clock signal and a feedback clock signal, determines a first phase difference between the time-delayed external clock signal and the feedback clock signal, and outputs a first phase error detecting signal; a second phase comparator that receives a first external clock signal and a time-delayed feedback clock signal, determines a second phase difference between the first external clock signal and the time-delayed feedback clock signal, and outputs a second phase error detecting signal; a phase compensator that inputs the first external clock signal and outputs a second external clock signal, wherein the phase compensator has a first mode of operation, in which the phase compensator phase-compensates the first external clock signal to generate the second external clock signal, and a second mode of operation, in which the phase compensator does not phase-compensate the first external clock signal, wherein the first and second modes are selectable based on the first and second phase error detecting signals; and a charge pump that generates a charge and adjusts a magnitude of the charge in response to the first and second phase error detecting signals.

Claim 7

The clock synchronizing circuit as claimed in claim 4 , wherein the phase compensator inputs the charge generated by the charge pump and, when the phase compensator is in the first mode of operation, compensates the phase of the first external clock signal in accordance with the magnitude of the charge from the charge pump.

Claim 8

The clock synchronizing circuit as claimed in claim 4 , further comprising an output buffer that receives the second external clock signal and outputs an internal clock signal.

Claim 9

The clock synchronizing circuit as claimed in claim 6 , wherein the feedback clock signal comprises a portion of the internal clock signal.

Claim 10

The clock synchronizing circuit as claimed in claim 4 , wherein the first phase comparator outputs a high level first phase error detecting signal if a phase of the time-delayed external clock signal is fast relative to a phase of the feedback clock signal, and outputs a low level first phase error detecting signal if the phase of the feedback clock signal is fast relative to the phase of the time-delayed external clock signal.

Claim 11

The clock synchronizing circuit as claimed in claim 8 , wherein the second phase comparator outputs a high level second phase error detecting signal if a phase of the first external clock signal is fast relative to a phase of the time-delayed feedback clock signal, and outputs a low level second phase error detecting signal if the phase of the time-delayed feedback clock signal is fast relative to the phase of the first external clock signal.

Claim 12

The clock synchronizing circuit as claimed in claim 4 , wherein the phase compensator slows down a phase of the first external clock signal when the first and second phase error detecting signals are both at a high level.

Claim 13

The clock synchronizing circuit as claimed in claim 4 , wherein the phase compensator speeds up a phase of the first external clock signal when the first and second phase error detecting signals are both at a low level.

Claim 14

The clock synchronizing circuit as claimed in claim 4 , wherein the phase compensator operates in the second mode and does not change a phase of the first external clock signal when the first phase error detecting signal is at a low level and the second phase error detecting signal is at a high level.

Claim 15

The clock synchronizing circuit as claimed in claim 4 , wherein the phase compensator operates in the second mode and does not change a phase of the first external clock signal when the first phase error detecting signal is at a high level and the second phase error detecting signal is at a low level.

Claim 18

The method of claim 14 , further comprising the step of generating an internal clock signal based on the phase-compensated external clock signal or the non-phase-compensated external clock signal.

Claim 19

The method of claim 15 , wherein the feedback clock signal is obtained from the internal clock signal.

Claim 20

The method of claim 14 , wherein the phase of the external clock signal and the phase of the feedback clock signal are substantially in phase when they are within plus or minus a predetermined delay time.

Claim 21

The method of claim 14 , wherein the phase of the external clock signal is not compensated when the external clock signal and the feedback clock signal are substantially 180 degrees out of phase.

Claim 22

The method of claim 14 , wherein the time-delayed external clock signal and the time-delayed feedback clock signal are time-delayed by an amount equal to approximately one-half of a predetermined clock jitter value.