US6500743B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of copper-polysilicon T-gate formation
Assignee: Advanced Micro Devices Inc
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Filing: 2000-08-30
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Granted: 2002-12-31
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Expires: 2020-08-30
Abstract
Abstract A method for manufacturing a field effect transistor ( 100 ) includes forming a gate structure ( 104 ) on a surface of a semiconductor substrate and forming first and second spacers ( 126, 126 ) on opposing sides of the gate structure. The method further includes etching a top portion of the gate structure and the first and second spacers to define a trench ( 1502 ). Subsequently, by a damascene process, at least a portion of the trench is filed with a barrier-high conductivity metal such as copper ( 1604 ) to form a T-gate.
Inventors
- 👤 Sergey Lopatin
- 👤 Steven C. Avanzino
- 👤 Matthew Buynoski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 09:52
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/01312; H10D64/01324; H10D64/017; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D64/664; H10P; H10P14/00; H10P14/40; H10P14/418; H10P14/46; H10W20/0698
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
112 words
A method for manufacturing a field effect transistor, the method comprising: forming a gate structure on a surface of a semiconductor substrate; forming first and second spacers on opposing sides of the gate structure; etching a top portion of the gate structure and the first and second spacers to define a trench; and by a damascene process, filling at least a portion of the trench with a high conductivity metal; wherein filling the at least a portion of the trench comprises: depositing a barrier material on an exposed portion of the gate structure and the first and second spacers; and depositing the high conductivity metal in the trench on the barrier material.
Claim 2
Independent Claim
112 words
A method for manufacturing a field effect transistor, the method comprising: forming a gate structure on a surface of a semiconductor substrate; forming first and second spacers on opposing sides of the gate structure; etching a top portion of the gate structure and the first and second spacers to define a trench; and by a damascene process, filling at least a portion of the trench with a high conductivity metal; wherein filling the at least a portion of the trench comprises: depositing a barrier material on an exposed portion of the gate structure and the first and second spacers; and depositing the high conductivity metal in the trench on the barrier material.
Claim 3
Dependent Claim
12 words
The method of claim 1 wherein the high conductivity metal comprises copper.
Claim 4
Dependent Claim
28 words
The method of claim 1 further comprising: exposing source drain regions of the field effect transistor adjacent the gate structure; depositing nickel on the semiconductor substrate; and annealing.
Claim 5
Dependent Claim
31 words
The method of claim 3 wherein annealing comprises: heating the semiconductor substrate to form a nickel alloy with the high conductivity metal and a nickel silicide on the source drain regions.
Claim 6
Dependent Claim
13 words
The method of claim 3 , wherein the high conductivity metal comprises copper.
Claim 7
Independent Claim
145 words
A method for manufacturing a field effect transistor, the method comprising: forming a gate structure on a surface of a semiconductor substrate in association with adjacent source/drain regions; forming first and second spacers on opposing sides of the gate structure; depositing a silicon nitride material on the surface of the semiconductor substrate including the adjacent source/drains to form a barrier on the adjacent source/drains; depositing a dielectric material on the surface of the semiconductor substrate; removing a portion of the gate structure, the spacers and the silicon nitride material to expose a top surface of the gate structure and the spacers; etching the gate structure, the spacers and the silicon nitride material to define a trench in the dielectric material defining contact openings for the adjacent source/drain regions in the dielectric material; and filling the trench and the contact openings with a high conductivity metal.
Claim 8
Independent Claim
145 words
A method for manufacturing a field effect transistor, the method comprising: forming a gate structure on a surface of a semiconductor substrate in association with adjacent source/drain regions; forming first and second spacers on opposing sides of the gate structure; depositing a silicon nitride material on the surface of the semiconductor substrate including the adjacent source/drains to form a barrier on the adjacent source/drains; depositing a dielectric material on the surface of the semiconductor substrate; removing a portion of the gate structure, the spacers and the silicon nitride material to expose a top surface of the gate structure and the spacers; etching the gate structure, the spacers and the silicon nitride material to define a trench in the dielectric material defining contact openings for the adjacent source/drain regions in the dielectric material; and filling the trench and the contact openings with a high conductivity metal.
Claim 9
Dependent Claim
12 words
The method of claim 6 wherein the high conductivity metal comprises copper.
Claim 10
Dependent Claim
22 words
The method of claim 6 wherein the act of removing comprises: etching the gate structure, the spacers and the silicon nitride material.
Claim 11
Dependent Claim
20 words
The method of claim 6 wherein the act of removing comprises: chemical mechanical polishing the surface of the semiconductor substrate.
Claim 12
Independent Claim
114 words
A method for manufacturing a semiconductor, the method comprising the acts of: on a semiconductor substrate, forming a polysilicon gate and adjacent source/drain regions; forming dielectric spacers on sides of the polysilicon gate; forming a masking layer on the surface of the semiconductor substrate, the masking layer having a thickness matching a height of the polysilicon gate; etching the polysilicon gate and the spacers to an etch depth to define a trench on a top surface of the polysilicon gate and the spacers and between inner walls of the masking layer; depositing a barrier material in the trench; and depositing copper on the barrier material in the trench to form a copper polysilicon gate.
Claim 13
Independent Claim
114 words
A method for manufacturing a semiconductor, the method comprising the acts of: on a semiconductor substrate, forming a polysilicon gate and adjacent source/drain regions; forming dielectric spacers on sides of the polysilicon gate; forming a masking layer on the surface of the semiconductor substrate, the masking layer having a thickness matching a height of the polysilicon gate; etching the polysilicon gate and the spacers to an etch depth to define a trench on a top surface of the polysilicon gate and the spacers and between inner walls of the masking layer; depositing a barrier material in the trench; and depositing copper on the barrier material in the trench to form a copper polysilicon gate.
Claim 14
Dependent Claim
25 words
The method of claim 10 further comprising the act of: after forming the masking layer, thinning the masking layer, the polysilicon gate and the spacers.
Claim 15
Dependent Claim
23 words
The method of claim 11 wherein the act of thinning comprises reactive ion etching the masking layer, the polysilicon gate and the spacers.
Claim 16
Dependent Claim
23 words
The method of claim 11 wherein the act of thinning comprises chemical mechanical polishing the masking layer, the silicide-polysilicon gate and the spacers.
Claim 17
Dependent Claim
26 words
The method of claim 10 wherein the barrier material comprises one of tantalum, tantalum nitride, tantalum silicon nitride, titanium nitride, titanium silicon nitride and tungsten nitride.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-12-30 | 2006-07-01 | 2006-12-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-12-30 | 2010-07-01 | 2010-12-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-12-30 | 2014-07-01 | 2014-12-31 | $7700.00 | Window Closed / Lapsed |