Patent US6492216B1 successfully refreshed from Google Patents.
US6492216B1
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Method of forming a transistor with a strained channel
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 2002-02-07
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Granted: 2002-12-10
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Expires: 2022-02-07
Abstract
Abstract A method of forming a tensile or compressive strained channel region for a semiconductor device, such as a MOSFET device, allowing improved carrier transport properties and increased device performance to be realized, has been developed. The method features the epitaxial growth of a semiconductor layer such as silicon, or silicon-germanium, with the incorporation of atoms such as carbon. The silicon-germanium-carbon channel layer, under biaxial tensile or compressive strain, is then overlaid with an optional silicon capping layer, used to accommodate the overlying, thermally grown silicon dioxide gate insulator layer, of the MOSFET device.
Inventors
- 👤 Yee-Chia Yeo
- 👤 Fu-Liang Yang
- 👤 Chenming Hu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 18:17
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/01; H10D62/021; H10D30/00; H10D30/01; H10D30/021; H10D30/0212; H10D30/60; H10D30/601; H10D30/608; H10D30/751; H10D30/791; H10D30/798; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D64/663
Claims Analysis
Total Claims: 35
Claim 1
Independent Claim
150 words
A method of fabricating a semiconductor device incorporated with a strained channel, on a semiconductor substrate, comprising the steps of: forming a semiconductor alloy layer on said semiconductor substrate, wherein said semiconductor alloy layer is comprised with a first element, a second element, and a third element; forming a gate insulator layer overlying said semiconductor alloy layer; forming a gate structure on said gate insulator layer forming insulator spacers on sides of said gate structure; forming source/drain regions in area of said semiconductor alloy layer and in an area of said semiconductor substrate not covered by said gate structure or by said insulator spacers; removing portions of said semiconductor alloy not covered by said gate structure or by said insulator spacers, exposing underlying portions of said semiconductor substrate comprised with said source/drain region; and forming metal silicide regions on said portions of said semiconductor substrate comprised with said source/drain region.
Claim 2
Independent Claim
150 words
A method of fabricating a semiconductor device incorporated with a strained channel, on a semiconductor substrate, comprising the steps of: forming a semiconductor alloy layer on said semiconductor substrate, wherein said semiconductor alloy layer is comprised with a first element, a second element, and a third element; forming a gate insulator layer overlying said semiconductor alloy layer; forming a gate structure on said gate insulator layer forming insulator spacers on sides of said gate structure; forming source/drain regions in area of said semiconductor alloy layer and in an area of said semiconductor substrate not covered by said gate structure or by said insulator spacers; removing portions of said semiconductor alloy not covered by said gate structure or by said insulator spacers, exposing underlying portions of said semiconductor substrate comprised with said source/drain region; and forming metal silicide regions on said portions of said semiconductor substrate comprised with said source/drain region.
Claim 3
Dependent Claim
21 words
The method of claim 1 , wherein said semiconductor alloy layer is a semiconductor alloy comprising of silicon, germanium, and carbon.
Claim 4
Dependent Claim
16 words
The method of claim 1 , wherein said semiconductor alloy is formed by epitaxial growth procedures.
Claim 5
Dependent Claim
37 words
The method of claim 1 , wherein said semiconductor alloy layer is obtained by an epitaxial growth of a second semiconductor alloy comprising of silicon and germanium, and implantation of carbon atoms into said second semiconductor alloy.
Claim 6
Dependent Claim
35 words
The method of claim 4 , wherein said semiconductor alloy layer has a natural lattice constant that is larger than that of said semiconductor substrate, so that said semiconductor alloy layer is under compressive strain.
Claim 7
Dependent Claim
35 words
The method of claim 4 , wherein said semiconductor alloy layer has a natural lattice constant that is smaller than that of said semiconductor substrate, so that said semiconductor alloy layer is under tensile strain.
Claim 8
Dependent Claim
37 words
The method of claim 1 , wherein said semiconductor alloy layer is silicon-germanium-carbon layer, denoted as Si (1−x−y) Ge x C y, wherein x is between 0 to 0.8 and y is between about 0 to 0.04.
Claim 9
Dependent Claim
21 words
The method of claim 1 , wherein the thickness of said semiconductor alloy layer is between about 20 to 500 Angstroms.
Claim 10
Dependent Claim
18 words
The method of claim 1 , wherein said gate insulator layer is a silicon dioxide gate insulator layer.
Claim 11
Dependent Claim
23 words
The method of claim 1 , wherein said gate insulator layer is thermally grown to a thickness between about 5 to 100 Angstroms.
Claim 12
Independent Claim
188 words
A method of fabricating a semiconductor device incorporated with a strained channel, on a semiconductor substrate, comprising the steps of: forming a semiconductor alloy layer on said semiconductor substrate, wherein said semiconductor alloy layer is comprised with a first element, a second element, and a third element; forming a semiconductor capping layer on said semiconductor alloy layer; forming a gate insulator layer overlying said semiconductor alloy layer; forming a gate structure on said gate insulator layer, with said gate structure comprised of a conductive layer and of underlying silicon capping layer; forming insulator spacers on sides of said gate structure; forming source/drain regions in portions of said silicon capping layer, portions of said semiconductor substrate, and in portions of said semiconductor alloy layer not covered by said gate structure of by said insulator spacers; selectively removing portions of said silicon capping layer, and portions of said semiconductor alloy layer not covered by said gate structure or by said insulator spacers, exposing underlying portions of said semiconductor substrate comprised with said source/drain regions; and forming metal silicide regions on portions of said semiconductor substrate comprised with said source/drain regions.
Claim 13
Independent Claim
188 words
A method of fabricating a semiconductor device incorporated with a strained channel, on a semiconductor substrate, comprising the steps of: forming a semiconductor alloy layer on said semiconductor substrate, wherein said semiconductor alloy layer is comprised with a first element, a second element, and a third element; forming a semiconductor capping layer on said semiconductor alloy layer; forming a gate insulator layer overlying said semiconductor alloy layer; forming a gate structure on said gate insulator layer, with said gate structure comprised of a conductive layer and of underlying silicon capping layer; forming insulator spacers on sides of said gate structure; forming source/drain regions in portions of said silicon capping layer, portions of said semiconductor substrate, and in portions of said semiconductor alloy layer not covered by said gate structure of by said insulator spacers; selectively removing portions of said silicon capping layer, and portions of said semiconductor alloy layer not covered by said gate structure or by said insulator spacers, exposing underlying portions of said semiconductor substrate comprised with said source/drain regions; and forming metal silicide regions on portions of said semiconductor substrate comprised with said source/drain regions.
Claim 14
Dependent Claim
25 words
The method of claim 11 , wherein said semiconductor alloy layer is a semiconductor alloy comprising silicon, germanium, and carbon, obtained by epitaxial growth procedures.
Claim 15
Dependent Claim
45 words
The method of claim 11 , wherein said semiconductor alloy layer is a semiconductor alloy comprising silicon, germanium, and carbon, obtained by epitaxial growth of a second semiconductor alloy comprising of silicon and germanium, and an implantation of carbon atoms into said second semiconductor alloy.
Claim 16
Dependent Claim
37 words
The method of claim 11 , wherein said semiconductor alloy layer is silicon-germanium-carbon, denoted as Si (1−x−y) Ge x C y, wherein x is between about 0 to 0.8, and y is between about 0 to 0.04.
Claim 17
Dependent Claim
35 words
The method of claim 14 , wherein said semiconductor alloy layer has a natural lattice constant that is larger than that of said semiconductor substrate, so that said semiconductor alloy layer is under compressive strain.
Claim 18
Dependent Claim
35 words
The method of claim 14 , wherein said semiconductor alloy layer has a natural lattice constant that is smaller than that of said semiconductor substrate, so that said semiconductor alloy layer is under tensile strain.
Claim 19
Dependent Claim
21 words
The method of claim 11 , wherein the thickness of said semiconductor alloy layer is between about 20 to 500 Angstroms.
Claim 20
Dependent Claim
18 words
The method of claim 11 , wherein said gate insulator layer is a silicon dioxide gate insulator layer.
Claim 21
Dependent Claim
23 words
The method of claim 11 , wherein said gate insulator layer is thermally grown to a thickness between about 5 to 100 Angstroms.
Claim 22
Dependent Claim
15 words
The method of claim 11 , wherein said semiconductor capping layer is comprised of silicon.
Claim 23
Dependent Claim
21 words
The method of claim 11 , wherein said semiconductor capping layer has a final thickness between about 10 to 100 Angstroms.
Claim 24
Independent Claim
204 words
A method of fabricating a semiconductor device on a semiconductor substrate, featuring a strained channel layer, comprising the steps of: forming isolation regions in a top portion of said semiconductor substrate; performing a first epitaxial growth procedure to selectively grow a strained channel layer on substantially the portions of said semiconductor substrate not occupied by said isolation regions; performing a second epitaxial growth procedure to selectively grow a capping layer on said channel layer; forming a gate insulator layer overlying said capping layer; forming a gate structure on said gate insulator layer, with said gate structure comprised of a conductive layer and of underlying silicon capping layer; forming insulator spacers on sides of said gate structure; forming source/drain regions in portions of said silicon capping layer, portions of said semiconductor substrate, and in portions of said semiconductor alloy layer, not covered by said gate structure or by said insulator spacers; selectively removing portions of said silicon capping layer, and portions of said semiconductor alloy layer not covered by said gate structure or by said insulator spacers, exposing underlying portions of said semiconductor substrate comprised with said source/drain regions; and forming metal silicide regions on portions of said semiconductor substrate comprised with said source/drain regions.
Claim 25
Independent Claim
204 words
A method of fabricating a semiconductor device on a semiconductor substrate, featuring a strained channel layer, comprising the steps of: forming isolation regions in a top portion of said semiconductor substrate; performing a first epitaxial growth procedure to selectively grow a strained channel layer on substantially the portions of said semiconductor substrate not occupied by said isolation regions; performing a second epitaxial growth procedure to selectively grow a capping layer on said channel layer; forming a gate insulator layer overlying said capping layer; forming a gate structure on said gate insulator layer, with said gate structure comprised of a conductive layer and of underlying silicon capping layer; forming insulator spacers on sides of said gate structure; forming source/drain regions in portions of said silicon capping layer, portions of said semiconductor substrate, and in portions of said semiconductor alloy layer, not covered by said gate structure or by said insulator spacers; selectively removing portions of said silicon capping layer, and portions of said semiconductor alloy layer not covered by said gate structure or by said insulator spacers, exposing underlying portions of said semiconductor substrate comprised with said source/drain regions; and forming metal silicide regions on portions of said semiconductor substrate comprised with said source/drain regions.
Claim 26
Dependent Claim
26 words
The method of claim 22 , wherein said strained channel layer is a semiconductor alloy layer comprising silicon, germanium, and carbon obtained by epitaxial growth procedures.
Claim 27
Dependent Claim
45 words
The method of claim 22 , wherein said strained channel layer is a semiconductor alloy layer comprising silicon, germanium, and carbon, obtained by epitaxial growth of a second semiconductor alloy comprising silicon and germanium, and an implantation of carbon atoms into said second semiconductor alloy.
Claim 28
Dependent Claim
37 words
The method of claim 22 , wherein said semiconductor alloy layer is silicon-germanium-carbon, denoted as Si (1−x−y) Ge x C y, wherein x is between about 0 to 0.8, and y is between about 0 to 0.04.
Claim 29
Dependent Claim
35 words
The method of claim 25 , wherein said semiconductor alloy layer has a natural lattice constant that is larger than that of said semiconductor substrate, so that said semiconductor alloy layer is under compressive strain.
Claim 30
Dependent Claim
35 words
The method of claim 25 , wherein said semiconductor alloy layer has a natural lattice constant that is smaller than that of said semiconductor substrate, so that said semiconductor alloy layer is under tensile strain.
Claim 31
Dependent Claim
21 words
The method of claim 22 , wherein the thickness of said semiconductor alloy layer is between about 20 to 500 Angstroms.
Claim 32
Dependent Claim
18 words
The method of claim 22 , wherein said gate insulator layer is a silicon dioxide gate insulator layer.
Claim 33
Dependent Claim
23 words
The method of claim 22 , wherein said gate insulator layer is thermally grown to a thickness between about 5 to 100 Angstroms.
Claim 34
Dependent Claim
15 words
The method of claim 22 , wherein said semiconductor capping layer is comprised of silicon.
Claim 35
Dependent Claim
21 words
The method of claim 22 , wherein said semiconductor capping layer has a final thickness between about 10 to 100 Angstroms.
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