Cache flush apparatus and computer system having the same

Claim 2

A cache flush apparatus for use in a computer having at least one processor provided with a copy-back type cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said at least one processor and said main memory, said cache flush apparatus comprising: update address storage means having a plurality of regions each of which has one or more entries for storing the address of data held in a dirty block; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data and storing the memory address MU as an update address in one of the entries of the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back and removing the update address which is equal to the memory address MW and is stored in an entry of the selected region; and flush executing means, in response to a request from said at least one processor, for issuing, to said system bus, a command for sequentially reading all update addresses stored in said update address storage means and writing-back into said main memory the data of the dirty block indicated by the update address read.

Claim 3

A cache flush apparatus according to claim 1 , in which the plural regions of said update address store means can be selected by the update address.

Claim 4

A cache flush apparatus for use in a computer having at least one processor provided with a copy-back type and direct map cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said at least one processor and said main memory, said cache flush apparatus comprising: update address storage means having a plurality of regions each of which corresponds to a cache block and has one entry for storing the memory address of data held in the corresponding cache block if the cache block's state is dirty; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data and storing the memory address MU as an update address in the entry of the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back, comparing the update address stored in the entry of the selected region with the write-back address and if they are the same, removing the update address; and flush executing means, in response to a request from said at least one processor, for issuing commands to said system bus each of which has the update address stored in the entry of a region and causes a write-back of data from the dirty block designated by the update address.

Claim 5

A cache flush apparatus for use in a computer having at least one processor provided with a copy-back type and direct map cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said at least one processor and said main memory, said cache flush apparatus comprising: update address storage means having a plurality of regions each of which corresponds to a cache block and has one entry for storing the memory address of data held in the corresponding cache block if the cache block's state is dirty; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data and storing the memory address MU as an update address in the entry of the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back, comparing the update address stored in the entry of the selected region with the write-back address and if they are the same, removing the update address; and flush executing means, in response to a request from said at least one processor, for issuing commands to said system bus each of which has the update address stored in the entry of a region and causes a write-back of data from the dirty block designated by the update address.

Claim 6

A cache flush apparatus for use in a computer having at least one processor provided with a copy-back type and direct map cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said at least one processor and said main memory, said cache flush apparatus comprising: update address storage means having a plurality of regions each of which corresponds to a cache block and has one entry and one counter; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data, storing the memory address MU as an update address in the entry of the selected region, and incrementing the counter of the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back, and decrementing the counter of the selected region; and flush executing means, in response to a request from said at least one processor, for issuing bus commands to said system bus each of which has the update address stored in the entry of a region with a non-initial counter value and causes a write-back of data from the dirty block designated by the update address.

Claim 7

A cache flush apparatus for use in a computer having at least one processor provided with a copy-back type and direct map cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said at least one processor and said main memory, said cache flush apparatus comprising: update address storage means having a plurality of regions each of which corresponds to a cache block and has one entry and one counter; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data, storing the memory address MU as an update address in the entry of the selected region, and incrementing the counter of the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back, and decrementing the counter of the selected region; and flush executing means, in response to a request from said at least one processor, for issuing bus commands to said system bus each of which has the update address stored in the entry of a region with a non-initial counter value and causes a write-back of data from the dirty block designated by the update address.

Claim 8

A cache flush apparatus for use in a computer having at least one processor provided with a copy-back type cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said at least one processor and said main memory, said cache flush apparatus comprising: update address storage means having a plurality of regions each of which has one or more entries for storing the addresses of data held in dirty blocks; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data, and storing the memory address MU as an update address in one of the entries of the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back and removing the update address in the selected region which coincides with the written-back address stored; and update address reading means for sequentially reading all of the update addresses stored in said update address storage means in order to make the update addresses be read by said at least one processor.

Claim 9

A cache flush apparatus for use in a computer having at least one processor provided with a copy-back type cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said at least one processor and said main memory, said cache flush apparatus comprising: update address storage means having a plurality of regions each of which has one or more entries for storing the addresses of data held in dirty blocks; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data, and storing the memory address MU as an update address in one of the entries of the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back and removing the update address in the selected region which coincides with the written-back address stored; and update address reading means for sequentially reading all of the update addresses stored in said update address storage means in order to make the update addresses be read by said at least one processor.

Claim 10

A cache flush apparatus for use in a computer having at least one processor provided with a copy-back type and direct map cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said at least one processor and said main memory, said cache flush apparatus comprising: update address storage means having a plurality of regions provided to correspond to cache blocks provided in said cache memory for storing an address of data stored in a dirty block which is a cache block among cache blocks and which stores data which must be written-back into said main memory, each region having one entry; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data, and storing the memory address MU as an update address in one of the entries of the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back, comparing the update address stored in the entry of the selected region with the write-back address, and if they are the same removing the update address from the entry; and update address reading means for sequentially reading all of the update addresses stored in said update address storage means in order to make the update addresses be read by said at least one processor.

Claim 11

A cache flush apparatus for use in a computer having at least one processor provided with a copy-back type and direct map cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said at least one processor and said main memory, said cache flush apparatus comprising: update address storage means having a plurality of regions provided to correspond to cache blocks provided in said cache memory for storing an address of data stored in a dirty block which is a cache block among cache blocks and which stores data which must be written-back into said main memory, each region having one entry; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data, and storing the memory address MU as an update address in one of the entries of the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back, comparing the update address stored in the entry of the selected region with the write-back address, and if they are the same removing the update address from the entry; and update address reading means for sequentially reading all of the update addresses stored in said update address storage means in order to make the update addresses be read by said at least one processor.

Claim 12

A cache flush apparatus for use in a computer having at least one processor provided with a copy-back type and direct map cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said at least one processor and said main memory, said cache flush apparatus comprising: update address storage means having a plurality of regions provided to correspond to cache blocks provided in said cache memory for storing an address of data stored in a dirty block which is a cache block among cache blocks which stores data which must be written-back into said main memory, each region having one entry and one counter; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data, storing the memory address MU as an update address in one of the entries of the selected region, and incrementing said counter corresponding to the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back, and decrementing said counter corresponding to the selected region; and update address reading means for sequentially reading update addresses stored in regions among the plural regions of said update address storage means for which a counter value is not an initial value and making the update addresses be read by said at least one processor.

Claim 13

A cache flush apparatus for use in a computer having at least one processor provided with a copy-back type and direct map cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said at least one processor and said main memory, said cache flush apparatus comprising: update address storage means having a plurality of regions provided to correspond to cache blocks provided in said cache memory for storing an address of data stored in a dirty block which is a cache block among cache blocks which stores data which must be written-back into said main memory, each region having one entry and one counter; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data, storing the memory address MU as an update address in one of the entries of the selected region, and incrementing said counter corresponding to the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back, and decrementing said counter corresponding to the selected region; and update address reading means for sequentially reading update addresses stored in regions among the plural regions of said update address storage means for which a counter value is not an initial value and making the update addresses be read by said at least one processor.

Claim 14

A cache flush apparatus for use in a computer having at least one processor provided with a copy-back type cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said at least one processor and said main memory, said cache flush apparatus comprising: update address storage means having a plurality of regions each of which has one or more entries for storing the addresses of data held in dirty blocks; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data and storing the memory address MU as an update address in one of the entries of the selected region; entry reclaiming means for comparing the number of empty entries of the region selected by said update address registering means with a predetermined value, selecting a stuffed entry of the selected region if the number of the empty entries is smaller than the predetermined value, issuing a bus command which causes a write-back of data stored in the cache block designated by the update address held in the selected entry, and changing the state of the selected entry from “stuffed” to “empty”; and flush executing means, in response to a request from said at least one processor, for issuing bus commands to said system bus each of which has one of the update addresses stored in said update address storage means and causes a write-back of data from the dirty block designated by the update address.

Claim 15

A cache flush apparatus according to claim 8 , in which said cache memory is an n-way set-associative type memory, and said plural regions of said update address storage means are provided to, one-to-one, correspond to groups each of which is formed by n cache blocks.

Claim 16

A cache flush apparatus according to claim 8 , in which the number of entries of each of the plural regions of said update address storage means is smaller than the number of the corresponding cache blocks.

Claim 17

A cache flush apparatus according to claim 8 , in which the plural regions of said update address storage means can be selected by the update address.

Claim 18

A cache flush apparatus according to claim 8 , in which said update address storage means comprises a dirty block counter for storing a number of dirty blocks corresponding to the regions storing an address of data which is stored as a dirty block; and said update address registering means comprises means for incrementing said dirty block counter corresponding to the selected region, and characterized by further comprising: decrement means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to the memory address MW at which the data has been written back and the identifier of the processor from which the date has been written back, and decrementing the dirty block counter of the selected region; and entry reclaiming means, when the value of a dirty block counter is made to an initial value as a result of a decrement performed by said decrement means, for making all the entries of the selected region empty.

Claim 19

A cache flush apparatus according to claim 12 , in which said entry reclaiming means, when the number of the update addresses stored in one of the plural regions of said update address storage means is larger than the count value of said dirty block counter corresponding to the region, selects one of the update addresses already stored in the region, issues a command for writing-back of data stored in the dirty block indicated by the selected update address into said main memory, and makes the entry in which the update address is stored to be an empty entry.

Claim 20

A cache flush apparatus for use in a computer having at least one processor provided with a copy-back type cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said at least one processor and said main memory, said cache flush apparatus comprising: update address storage means having a plurality of regions each of which has one or more entries for storing the addresses of data held in dirty blocks; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data, and storing the memory address MU as an update address in one of the entries of the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back, detecting, for a predetermined time, whether or not an update address which coincides with the write-back address exists in the selected region, and removing the update address which coincides with the write-back address; entry reclaiming means for comparing the number of the empty entries of the region selected by said update address registering means with a predetermined value, selecting a stuffed entry of the selected region if the number of the empty entries is smaller than the predetermined value, issuing a bus command which causes a write-back of data stored in the cache block designated by the update address held in the selected entry, and changing the state of the selected entry from “stuffed” to “empty”; and flush executing means, in response to a request from said at least one processor, for issuing bus commands to said system bus each of which has one of the update addresses stored in said update address storage means and causes a write-back of data from the dirty block designated by the update address.

Claim 21

A cache flush apparatus according to claim 14 , in which said update address removing means, upon detecting that a cache block storing data of a given address is not a dirty block, selects one of the plural regions of said update address storage means based on the given address and, when it detects an update command coincides with the update address in the selected region, removes the update address.

Claim 22

A cache flush apparatus according to claim 14 , in which the number of entries of each of the plural regions of said update address storage means is smaller than the number of the corresponding cache blocks.

Claim 23

A cache flush apparatus according to claim 14 , in which the plural regions of said update address storage means can be selected by the update address.

Claim 24

A cache flush apparatus according to claim 14 , in which said update address storage means comprises a dirty block counter for storing a number of dirty blocks corresponding to the regions storing an address of data which is stored as a dirty block; said update address registering means comprises means for incrementing said dirty block counter corresponding to the selected region; said update address removing means comprises means for decrementing said dirty block counter corresponding to the selected region, and characterized by further comprising: removing means for removing all of the update addresses stored in the region corresponding to said dirty block counter when said dirty block counter is made to be an initial value as a result of a decrement performed by said decrement means.

Claim 25

A cache flush apparatus for use in a computer having at least one processor provided with a copy-back type cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said at least one processor and said main memory, said cache flush apparatus comprising: update address storage means having a plurality of regions each of which has one or more entries for storing the addresses of data held in dirty blocks; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data, and storing the memory address MU as an update address in one of the entries of the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block into said main memory, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back, determining whether or not an update address which coincides with the write-back address exists in the selected region until said cache flush apparatus detects a command which must be processed next, and removing the update address when an update address which coincides with the write-back address is detected; entry reclaiming means for comparing a number of empty entries of the region selected by said update address registering means with a predetermined value, selecting a stuffed entry of the selected region if the number of the empty entries is smaller than the predetermined value, issuing a bus command which causes a write-back of data stored in the cache block designated by the update address held in the selected entry, and changing the state of the selected entry from “stuffed” to “empty”; and flush executing means, in response to a request from said at least one processor, for issuing bus commands to said system bus each of which has one of the update addresses stored in said update address storage means and causes a write-back of data from the dirty block designated by the update address.

Claim 26

A cache flush apparatus according to claim 19 , in which when said update address removing means detects a command indicating that all cache blocks for storing data indicated by a certain address are not dirty blocks, said update address removing means selects one of the plural regions of said update address storage means in accordance with the certain address, retrieves the selected region, and removes the update address when an update address which coincides with the write-back address is detected.

Claim 27

A cache flush apparatus according to claim 19 , in which the number of entries of each of the plural regions of said update address storage means is smaller than the number of the corresponding cache blocks.

Claim 28

A cache flush apparatus according to claim 19 , in which the plural regions of said update address storage means can be selected by the update address.

Claim 29

A cache flush apparatus according to claim 19 , in which said update address storage means comprises a dirty block counter for storing a number of dirty blocks corresponding to the regions storing an address of data which is stored as a dirty block; said update address registering means comprises means for incrementing said dirty block counter corresponding to the selected regions; said update address removing means comprises means for decrementing said dirty block counter corresponding to the selected region, and characterized by further comprising: removing means for removing all of the update addresses stored in the region corresponding to said dirty block counter when said dirty block counter is made to be an initial value as a result of a decrement performed by said decrement means.

Claim 30

A computer system having processors provided with a copy-back type cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said processors and said main memory and arranged to periodically extract a checkpoint for restarting an interrupted process, comprising: a cache flush apparatus comprising: update address storage means having a plurality of regions each of which has one or more entries for storing the addresses of data held in dirty blocks; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data and storing the memory address MU as an update address in one of the entries of the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according address MW at which the data has been written back and an identifier of a processor from which the data has been written back and removing the update address which is equal to the memory address stored in an entry of the selected region; and flush executing means, in response to a request from any of said processors, for issuing, to said system bus, a command for sequentially reading all update addresses stored in said update address storage means and writing-back into said main memory the data of the dirty block indicated by the update address read; normal data processing means for performing normal data processing while causing said cache flush apparatus to acquire an update address; checkpoint acquisition means including means for storing into said main memory the context of a data process which is synchronously performed by said processors and writing-back, into said main memory, of data stored in all of the dirty blocks by said flush executing means of said cache flush apparatus; and rollback & recovery means for restoring said main memory to a previous checkpoint when a fault has taken place and using information stored in said restored main memory to restart the normal data processing.

Claim 31

A computer system having processors provided with a copy-back type cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said processors and said main memory and arranged to periodically extract a checkpoint for restarting an interrupted process, comprising: a cache flush apparatus comprising: update address storage means having a plurality of regions each of which has one or more entries for storing the addresses of data held in dirty blocks; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data and storing the memory address MU as an update address in one of the entries of the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according address MW at which the data has been written back and an identifier of a processor from which the data has been written back and removing the update address which is equal to the memory address stored in an entry of the selected region; and flush executing means, in response to a request from any of said processors, for issuing, to said system bus, a command for sequentially reading all update addresses stored in said update address storage means and writing-back into said main memory the data of the dirty block indicated by the update address read; normal data processing means for performing normal data processing while causing said cache flush apparatus to acquire an update address; checkpoint acquisition means including means for storing into said main memory the context of a data process which is synchronously performed by said processors and writing-back, into said main memory, of data stored in all of the dirty blocks by said flush executing means of said cache flush apparatus; and rollback & recovery means for restoring said main memory to a previous checkpoint when a fault has taken place and using information stored in said restored main memory to restart the normal data processing.

Claim 32

A computer system according to claim 24 , in which the plural regions of said update address storage means can be selected by the update address.

Claim 33

A computer system having processors provided with a copy-back type cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said processors and said main memory and arranged to periodically extract a checkpoint for restarting an interrupted process, comprising: a cache flush apparatus comprising: update address storage means having a plurality of regions provided to correspond to cache blocks provided in said cache memory for storing an address of data stored in a dirty block, each region having one entry; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data and storing the memory address MU as an update address in one of the entries of the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back, comparing the update address stored in the entry of the selected region with the write-back address and if they are the same, removing the update address from the entry; and flush executing means, in response to a request from any of said processors, for issuing, to said system bus, a command for sequentially reading all update addresses stored in said update address storage means and writing-back into said main memory data of the dirty block indicated by the update address read; normal data processing means for performing normal data processing while causing said cache flush apparatus to acquire an update address; checkpoint acquisition means including means for storing into said main memory the context of a data process which is synchronously performed by said processors and writing-back, into said main memory, of data stored in all of the dirty blocks by said flush executing means of said cache flush apparatus; and rollback & recovery means for restoring said main memory to a previous checkpoint when a fault has taken place and using information stored in said restored main memory to restart the normal data processing.

Claim 34

A computer system having processors provided with a copy-back type cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said processors and said main memory and arranged to periodically extract a checkpoint for restarting an interrupted process, comprising: a cache flush apparatus comprising: update address storage means having a plurality of regions provided to correspond to cache blocks provided in said cache memory for storing an address of data stored in a dirty block, each region having one entry; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data and storing the memory address MU as an update address in one of the entries of the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back, comparing the update address stored in the entry of the selected region with the write-back address and if they are the same, removing the update address from the entry; and flush executing means, in response to a request from any of said processors, for issuing, to said system bus, a command for sequentially reading all update addresses stored in said update address storage means and writing-back into said main memory data of the dirty block indicated by the update address read; normal data processing means for performing normal data processing while causing said cache flush apparatus to acquire an update address; checkpoint acquisition means including means for storing into said main memory the context of a data process which is synchronously performed by said processors and writing-back, into said main memory, of data stored in all of the dirty blocks by said flush executing means of said cache flush apparatus; and rollback & recovery means for restoring said main memory to a previous checkpoint when a fault has taken place and using information stored in said restored main memory to restart the normal data processing.

Claim 35

A computer system having processors provided with a copy-back type cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said processors and said main memory and arranged to periodically extract a checkpoint for restarting an interrupted process, comprising: a cache flush apparatus comprising: update address storage means having a plurality of regions provided to correspond to cache blocks provided in said cache memory for storing an address of data stored in a dirty block, each region having one entry and one counter; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data, storing the memory address MU as an update address in one of the entries of the selected region, and incrementing said counter corresponding to the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back, and decrementing said counter corresponding to the selected region; and flush executing means, in response to a request from any of said processors, for issuing, to said system bus, a command for sequentially reading update addresses stored in regions among the regions of said update address storage means of which count value is not an initial value, and writing-back into said main memory data of the dirty block indicated by the update address read; normal data processing means for performing normal data processing while causing said cache flush apparatus to acquire an update address; checkpoint acquisition means including means for storing into said main memory the context of a data process which is synchronously performed by said processors and writing-back, into said main memory, of data stored in all of the dirty blocks by said flush executing means of said cache flush apparatus; and rollback & recovery means for restoring said main memory to a previous checkpoint when a fault has taken place and using information stored in said restored main memory to restart the normal data processing.

Claim 36

A computer system having processors provided with a copy-back type cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said processors and said main memory and arranged to periodically extract a checkpoint for restarting an interrupted process, comprising: a cache flush apparatus comprising: update address storage means having a plurality of regions provided to correspond to cache blocks provided in said cache memory for storing an address of data stored in a dirty block, each region having one entry and one counter; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data, storing the memory address MU as an update address in one of the entries of the selected region, and incrementing said counter corresponding to the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back, and decrementing said counter corresponding to the selected region; and flush executing means, in response to a request from any of said processors, for issuing, to said system bus, a command for sequentially reading update addresses stored in regions among the regions of said update address storage means of which count value is not an initial value, and writing-back into said main memory data of the dirty block indicated by the update address read; normal data processing means for performing normal data processing while causing said cache flush apparatus to acquire an update address; checkpoint acquisition means including means for storing into said main memory the context of a data process which is synchronously performed by said processors and writing-back, into said main memory, of data stored in all of the dirty blocks by said flush executing means of said cache flush apparatus; and rollback & recovery means for restoring said main memory to a previous checkpoint when a fault has taken place and using information stored in said restored main memory to restart the normal data processing.

Claim 37

A computer system having processors provided with a copy-back type cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said processors and said main memory and arranged to periodically extract a checkpoint for restarting an interrupted process, comprising: a cache flush apparatus comprising: update address storage means having a plurality of regions each of which has one or more entries for storing the addresses of data held in dirty blocks; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated an identifier of a processor which has updated the data and storing the memory address MU as an update address in one of the entries of the selected region; and flush executing means, in response to a request from any of said processors, for issuing bus commands to said system bus each of which has one of the update addresses stored in said update address storage means and causes a write-back of data from the dirty block designated by the update address; normal data processing means for performing normal data processing while causing said cache flush apparatus to acquire an update address; checkpoint acquisition means including means for storing into said main memory the context of a data process which is synchronously performed by said processors and writing-back, into said main memory, of data stored in all of the dirty blocks by said flush executing means of said cache flush apparatus; and rollback & recovery means for restoring said main memory to a previous checkpoint when a fault has taken place and using information stored in said restored main memory to restart the normal data processing.

Claim 38

A computer system having processors provided with a copy-back type cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said processors and said main memory and arranged to periodically extract a checkpoint for restarting an interrupted process, comprising: a cache flush apparatus comprising: update address storage means having a plurality of regions each of which has one or more entries for storing the addresses of data held in dirty blocks; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated an identifier of a processor which has updated the data and storing the memory address MU as an update address in one of the entries of the selected region; and flush executing means, in response to a request from any of said processors, for issuing bus commands to said system bus each of which has one of the update addresses stored in said update address storage means and causes a write-back of data from the dirty block designated by the update address; normal data processing means for performing normal data processing while causing said cache flush apparatus to acquire an update address; checkpoint acquisition means including means for storing into said main memory the context of a data process which is synchronously performed by said processors and writing-back, into said main memory, of data stored in all of the dirty blocks by said flush executing means of said cache flush apparatus; and rollback & recovery means for restoring said main memory to a previous checkpoint when a fault has taken place and using information stored in said restored main memory to restart the normal data processing.

Claim 39

A computer system according to claim 28 , in which said cache memory is an n-way set-associative type memory, and said plural regions of said update address storage means are provided to, one-to-one, correspond to groups each of which is formed by n cache blocks.

Claim 40

A computer system according to claim 28 , in which the number of entries of each of the plural regions of said update address storage means is smaller than the number of the corresponding cache blocks.

Claim 41

A computer system according to claim 28 , in which the plural regions of said update address storage means can be selected by the update address.

Claim 42

A computer system according to claim 28 , in which said update address storage means comprises a dirty block counter for storing a number of dirty blocks corresponding to the regions storing an address of data which is stored as a dirty block; and said update address registering means comprises means for incrementing said dirty block counter corresponding to the selected region, and characterized by further comprising: decrement means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to the memory address MW at which the data has been written back and the identifier of the processor from which the date has been written back, and decrementing the dirty block counter of the selected region; and entry reclaiming means, when the value of a dirty block counter is made to an initial value as a result of a decrement performed by said decrement means, for making all the entries of the selected region empty.

Claim 43

A computer system according to claim 32 , in which said entry reclaiming means, when the number of the update addresses stored in one of the plural regions of said update address storage means is larger than the count value of said dirty block counter corresponding to the region, selects one of the update addresses already stored in the region, issues a command for write-back of data stored in the dirty block indicated by the selected update address into said main memory, and makes the entry in which the update address is stored to be an empty entry.

Claim 44

A computer system having processors provided with a copy-back type cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said processors and said main memory and arranged to periodically extract a checkpoint for restarting an interrupted process, comprising: a cache flush apparatus comprising: update address storage means having a plurality of regions each of which has one or more entries for storing the addresses of data held in dirty blocks; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated an identifier of a processor which has updated the data, and storing the memory address MU as an update address in one of the entries of the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back, detecting, for a predetermined time, whether or not an update address which coincides with the write-back address exists in the selected region, and removing the update address which coincides with the write-back address; entry reclaiming means for comparing the number of empty entries of the region selected by said update address registering means with a predetermined value, selecting a stuffed entry of the selected region if the number of the empty entries is smaller than the predetermined value, issuing a bus command which causes a write-back of data stored in the cache block designated by the update address of the entry, and changing the state of the entry from “stuffed” to “empty”; and flush executing means, in response to a request from any of said processors, for issuing bus commands to said system bus each of which has one of the update addresses stored in said update address storage means and causes a write-back of data from the dirtyblock designated by the update address; normal data processing means for performing normal data processing while causing said cache flush apparatus to acquire an update address; checkpoint acquisition means including means for storing into said main memory the context of a data process which is synchronously performed by said processors and writing-back, into said main memory, of data stored in all of the dirty blocks by said flush executing means of said cache flush apparatus; and rollback & recovery means for restoring said main memory to a previous checkpoint when a fault has taken place and using information stored in said restored main memory to restart the normal data processing.

Claim 45

A computer system according to claim 34 , in which said update address removing means, upon detecting that a cache block storing data of a given address is not a dirty block, selects one of the plural regions of said update address storage means based on the given address and, when it detects an update command coincides with the update address in the selected region, removes the update address.

Claim 46

A computer system according to claim 34 , in which the number of entries of each of the plural regions of said update address storage means is smaller than the number of the corresponding cache blocks.

Claim 47

A computer system according to claim 34 , in which the plural regions of said update address storage means can by selected by the update address.

Claim 48

A computer system according to claim 34 , in which said update address storage means comprises a dirty block counter for storing a number of dirty blocks corresponding to the regions storing an address of data which is stored as a dirty block; said update address registering means comprises means for incrementing said dirty block counter corresponding to the selected region; said update address removing means comprises means for decrementing said dirty block counter corresponding to the selected region, and characterized by further comprising: removing means for removing all of the update addresses stored in the region corresponding to said dirty block counter when said dirty block counter is made to be an initial value as a result of a decrement performed by said decrement means.

Claim 49

A computer system having processors provided with a copy-back type cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said processors and said main memory and arranged to periodically extract a checkpoint for restarting an interrupted process, comprising: a cache flush apparatus comprising: update address storage means having a plurality of regions each of which has one or more entries for storing the addresses of data held in dirty blocks; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data, and storing the memory address MU as an update address in one of the entries of the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block into said main memory, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back, determining whether or not an update address which coincides with the write-back address exists in the selected region until said cache flush apparatus detects a command which must be processed next, and removing the update address when an update address which coincides with the write-back address is detected; entry reclaiming means for comparing a number of empty entries of the region selected by said update address registering means with a predetermined value, selecting a stuffed entry of the selected region if the number of the empty entries is smaller than the predetermined value, issuing a bus command which causes a write-back of data stored in the cache block designated by the update address held in the selected entry, and changing the state of the entry from “stuffed” to “empty”; and flush executing means, in response to a request from any of said processors, for issuing bus commands to said system bus each of which has one of the update addresses stored in said update address storage means and causes a write-back of data from the dirty block designated by the update address; normal data processing means for performing normal data processing while causing said cache flush apparatus to acquire an update address; checkpoint acquisition means including means for storing into said main memory the context of a data process which is synchronously performed by said processors and writing-back, into said main memory, of data stored in all of the dirty blocks by said flush executing means of said cache flush apparatus; and rollback & recovery means for restoring said main memory to a previous checkpoint when a fault has taken place and using information stored in said restored main memory to restart the normal data processing.

Claim 50

A computer system according to claim 39 , in which when said update address removing means detects a command indicating that all cache blocks for storing data indicated by a certain address are not dirty blocks said update address removing means selects one of the plural regions of said update address storage means in accordance with the certain address, retrieves the selected region, and removes the update address when an update address which coincides with the write-back address is detected.

Claim 51

A computer system according to claim 39 , in which the number of entries of each of the plural regions of said update address storage means is smaller than the number of the corresponding cache blocks.

Claim 52

A computer system according to claim 39 , in which the plural regions of said update address storage means can be selected by the update address.

Claim 53

A computer system according to claim 39 , in which said update address storage means comprises a dirty block counter for storing a number of dirty blocks corresponding to the regions storing an address of data which is stored as a dirty block; said update address registering means comprises means for incrementing said dirty block counter corresponding to the selected regions; said update address removing means comprises means for decrementing said dirty block counter corresponding to the selected region, and characterized by further comprising: removing means for removing all of the update addresses stored in the region corresponding to said dirty block counter when said dirty block counter is made to be an initial value as a result of a decrement performed by said decrement means.

Claim 54

A computer system having processors provided with a copy-back type cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said processors and said main memory and arranged to periodically extract a checkpoint for restarting an interrupted process, comprising: a cache flush apparatus comprising: update address storage means having a plurality of regions each of which has one or more entries for storing the addresses of data held in dirty blocks; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data, and storing the memory address MU as an update address in one of the entries of the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back and removing the update address in the selected region which coincides with the written-back address stored; and update address reading means for sequentially reading all of the update addresses stored in said update address storage means in order to make the update addresses be read by said processors; normal data processing means for performing normal data processing while causing said cache flush apparatus to acquire an update address; checkpoint acquisition means including means for storing into said main memory the context of a data process which is synchronously performed by said processors and writing-back, into said main memory, of data stored in all of the dirty blocks by obtaining the update address through said update address reading means of said cache flush apparatus and by performing a command for writing-back data indicated by the identified update address from said cache memory into said main memory; and rollback & recovery means for restoring said main memory to a previous checkpoint when a fault has taken place and using information stored in said restored main memory to restart the normal data processing.

Claim 55

A computer system having processors provided with a copy-back type cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said processors and said main memory and arranged to periodically extract a checkpoint for restarting an interrupted process, comprising: a cache flush apparatus comprising: update address storage means having a plurality of regions each of which has one or more entries for storing the addresses of data held in dirty blocks; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data, and storing the memory address MU as an update address in one of the entries of the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back and removing the update address in the selected region which coincides with the written-back address stored; and update address reading means for sequentially reading all of the update addresses stored in said update address storage means in order to make the update addresses be read by said processors; normal data processing means for performing normal data processing while causing said cache flush apparatus to acquire an update address; checkpoint acquisition means including means for storing into said main memory the context of a data process which is synchronously performed by said processors and writing-back, into said main memory, of data stored in all of the dirty blocks by obtaining the update address through said update address reading means of said cache flush apparatus and by performing a command for writing-back data indicated by the identified update address from said cache memory into said main memory; and rollback & recovery means for restoring said main memory to a previous checkpoint when a fault has taken place and using information stored in said restored main memory to restart the normal data processing.

Claim 56

A computer system having processors provided with a copy-back type cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said processors and said main memory and arranged to periodically extract a checkpoint for restarting an interrupted process, comprising: a cache flush apparatus comprising: update address storage means having a plurality of regions provided to correspond to cache blocks provided in said cache memory for storing an address of data stored in a dirty block which is a cache block among cache blocks and which stores data which must be written-back into said main memory, each region having one entry; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data, and storing the memory address MU as an update address in one of the entries of the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back, the update address stored in the entry of the selected region with the write-back address, and if they are the same removing the update address from the entry; and update address reading means for sequentially reading all of the update addresses stored in said update address storage means in order to make the update addresses be read by said processors; normal data processing means for performing normal data processing while causing said cache flush apparatus to acquire an update address; checkpoint acquisition means including means for storing into said main memory the context of a data process which is synchronously performed by said processors and writing-back, into said main memory, of data stored in all of the dirty blocks by obtaining the update address through said update address reading means of said cache flush apparatus and by performing a command for writing-back data indicated by the identified update address from said cache memory into said main memory; and rollback & recovery means for restoring said main memory to a previous checkpoint when a fault has taken place and using information stored in said restored main memory to restart the normal data processing.

Claim 57

A computer system having processors provided with a copy-back type cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said processors and said main memory and arranged to periodically extract a checkpoint for restarting an interrupted process, comprising: a cache flush apparatus comprising: update address storage means having a plurality of regions provided to correspond to cache blocks provided in said cache memory for storing an address of data stored in a dirty block which is a cache block among cache blocks and which stores data which must be written-back into said main memory, each region having one entry; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data, and storing the memory address MU as an update address in one of the entries of the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back, the update address stored in the entry of the selected region with the write-back address, and if they are the same removing the update address from the entry; and update address reading means for sequentially reading all of the update addresses stored in said update address storage means in order to make the update addresses be read by said processors; normal data processing means for performing normal data processing while causing said cache flush apparatus to acquire an update address; checkpoint acquisition means including means for storing into said main memory the context of a data process which is synchronously performed by said processors and writing-back, into said main memory, of data stored in all of the dirty blocks by obtaining the update address through said update address reading means of said cache flush apparatus and by performing a command for writing-back data indicated by the identified update address from said cache memory into said main memory; and rollback & recovery means for restoring said main memory to a previous checkpoint when a fault has taken place and using information stored in said restored main memory to restart the normal data processing.

Claim 58

A computer system having processors provided with a copy-back type cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said processors and said main memory and arranged to periodically extract a checkpoint for restarting an interrupted process, comprising: a cache flush apparatus comprising: update address storage means having a plurality of regions provided to correspond to cache blocks provided in said cache memory for storing an address of data stored in a dirty block which is a cache block among cache blocks which stores data which must be written-back into said main memory, each region having one entry and one counter; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data, storing the memory address MU as an update address in one of the entries of the selected region, and incrementing said counter corresponding to the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back, and decrementing said counter corresponding to the selected region; and update address reading means for sequentially reading update addresses stored in regions among the plural regions of said update address storage means for which a counter value is not an initial value and making the update addresses be read by said processors; normal data processing means for performing normal data processing while causing said cache flush apparatus to acquire an update address; checkpoint acquisition means including means for storing into said main memory the context of a data process which is synchronously performed and writing-back, into said main memory, of data stored in all of the dirty blocks by obtaining the update address through said update address reading means of said cache flush apparatus and by performing a command for writing-back data indicated by the identified update address from said cache memory into said main memory; and rollback & recovery means for restoring said main memory to a previous checkpoint when a fault has taken place and using information stored in said restored main memory to restart the normal data processing.

Claim 59

A computer system having processors provided with a copy-back type cache memory having a bus snoop mechanism, a main memory and a system bus for connecting said processors and said main memory and arranged to periodically extract a checkpoint for restarting an interrupted process, comprising: a cache flush apparatus comprising: update address storage means having a plurality of regions provided to correspond to cache blocks provided in said cache memory for storing an address of data stored in a dirty block which is a cache block among cache blocks which stores data which must be written-back into said main memory, each region having one entry and one counter; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data, storing the memory address MU as an update address in one of the entries of the selected region, and incrementing said counter corresponding to the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back, and decrementing said counter corresponding to the selected region; and update address reading means for sequentially reading update addresses stored in regions among the plural regions of said update address storage means for which a counter value is not an initial value and making the update addresses be read by said processors; normal data processing means for performing normal data processing while causing said cache flush apparatus to acquire an update address; checkpoint acquisition means including means for storing into said main memory the context of a data process which is synchronously performed and writing-back, into said main memory, of data stored in all of the dirty blocks by obtaining the update address through said update address reading means of said cache flush apparatus and by performing a command for writing-back data indicated by the identified update address from said cache memory into said main memory; and rollback & recovery means for restoring said main memory to a previous checkpoint when a fault has taken place and using information stored in said restored main memory to restart the normal data processing.

Claim 60

A computer system having at least first and second computers and arranged to periodically extract a checkpoint for restarting an interrupted process, the system comprising: memory update monitoring means for acquiring a write command generated in said first computer, storing the write command to a main memory and transmitting a stored command to said second computer when it is instructed by said first computer; and memory update means for receiving the command transmitted by said memory update monitoring means to issue a write command, similar to that for said first computer, into a main memory of said second computer, wherein said first computer comprises: a plurality of processors and a system bus; a cache flush apparatus comprising: update address storage means having a plurality of regions each of which has one or more entries for storing the addresses of data held in dirty blocks; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data and storing the memory address MU as an update address in one of the entries of the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back and removing the update address which is equal to the memory address stored in an entry of the selected region; and flush executing means, in response to a request from any of said processors for issuing, to said system bus, a command for sequentially reading all update addresses stored in said update address storage means and writing-back into said main memory the data of the dirty block indicated by the update address read; normal data processing means for performing normal data processing while causing said cache flush apparatus to acquire an update address; checkpoint acquisition means including means for storing into said main memory the context of a data process which is synchronously performed and writing-back, into said main memory, data stored in all of the dirty blocks performed by said flush executing means of said cache flush apparatus, and issuing a command for transmitting the stored commands to said second computer; and said second computer comprises waiting means for starting the normal data processing when said memory update means does not receive a command from said memory update monitoring means.

Claim 61

A computer system having at least first and second computers and arranged to periodically extract a checkpoint for restarting an interrupted process, the system comprising: memory update monitoring means for acquiring a write command generated in said first computer, storing the write command to a main memory and transmitting a stored command to said second computer when it is instructed by said first computer; and memory update means for receiving the command transmitted by said memory update monitoring means to issue a write command, similar to that for said first computer, into a main memory of said second computer, wherein said first computer comprises: a plurality of processors and a system bus; a cache flush apparatus comprising: update address storage means having a plurality of regions each of which has one or more entries for storing the addresses of data held in dirty blocks; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data and storing the memory address MU as an update address in one of the entries of the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back and removing the update address which is equal to the memory address stored in an entry of the selected region; and flush executing means, in response to a request from any of said processors for issuing, to said system bus, a command for sequentially reading all update addresses stored in said update address storage means and writing-back into said main memory the data of the dirty block indicated by the update address read; normal data processing means for performing normal data processing while causing said cache flush apparatus to acquire an update address; checkpoint acquisition means including means for storing into said main memory the context of a data process which is synchronously performed and writing-back, into said main memory, data stored in all of the dirty blocks performed by said flush executing means of said cache flush apparatus, and issuing a command for transmitting the stored commands to said second computer; and said second computer comprises waiting means for starting the normal data processing when said memory update means does not receive a command from said memory update monitoring means.

Claim 62

A computer system according to claim 47 , in which the plural regions of said update address storage means can be selected by the update address.

Claim 63

A computer system having at least first and second computers and arranged to periodically extract a checkpoint for restarting an interrupted process, the system comprising: memory update monitoring means for acquiring a write command generated in said first computer, storing the write command to a main memory and transmitting a stored command to said second computer when it is instructed by said first computer; and memory update means for receiving the command transmitted by said memory update monitoring means to issue a write command, similar to that for said first computer, into a main memory of said second computer, wherein said first computer comprises: a plurality of processors and a system bus; a cache flush apparatus comprising: update address storage means having a plurality of regions provided to correspond to cache blocks provided in said cache memory for storing an address of data stored in a dirty block, each region having one entry; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data and storing the memory address MU as an update address in one of the entries of the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back, comparing the update address stored in the entry of the selected region with the write-back address and removing the update address stored in the selected region when the update address and the memory address are the same; and flush executing means, in response to a request from any of said processors, for issuing, to said system bus, a command for sequentially reading all of update addresses stored in said update address storage means and writing-back into said main memory data of the dirty block indicated by the update address read; normal data processing means for performing normal data processing while causing said cache flush apparatus to acquire an update address; checkpoint acquisition means including means for storing into said main memory the context of a data process which is synchronously performed and writing-back, into said main memory, data stored in all of the dirty blocks performed by said flush executing means of said cache flush apparatus, and issuing a command for transmitting the stored commands to said second computer; and said second computer comprises waiting means for starting the normal data processing when said memory update means does not receive a command from said memory update monitoring means.

Claim 64

A computer system having at least first and second computers and arranged to periodically extract a checkpoint for restarting an interrupted process, the system comprising: memory update monitoring means for acquiring a write command generated in said first computer, storing the write command to a main memory and transmitting a stored command to said second computer when it is instructed by said first computer; and memory update means for receiving the command transmitted by said memory update monitoring means to issue a write command, similar to that for said first computer, into a main memory of said second computer, wherein said first computer comprises: a plurality of processors and a system bus; a cache flush apparatus comprising: update address storage means having a plurality of regions provided to correspond to cache blocks provided in said cache memory for storing an address of data stored in a dirty block, each region having one entry; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data and storing the memory address MU as an update address in one of the entries of the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back, comparing the update address stored in the entry of the selected region with the write-back address and removing the update address stored in the selected region when the update address and the memory address are the same; and flush executing means, in response to a request from any of said processors, for issuing, to said system bus, a command for sequentially reading all of update addresses stored in said update address storage means and writing-back into said main memory data of the dirty block indicated by the update address read; normal data processing means for performing normal data processing while causing said cache flush apparatus to acquire an update address; checkpoint acquisition means including means for storing into said main memory the context of a data process which is synchronously performed and writing-back, into said main memory, data stored in all of the dirty blocks performed by said flush executing means of said cache flush apparatus, and issuing a command for transmitting the stored commands to said second computer; and said second computer comprises waiting means for starting the normal data processing when said memory update means does not receive a command from said memory update monitoring means.

Claim 65

A computer system having at least first and second computers and arranged to periodically extract a checkpoint for restarting an interrupted process, the system comprising: memory update monitoring means for acquiring a write command generated in said first computer, storing the write command to a main memory and transmitting a stored command to said second computer when it is instructed by said first computer; and memory update means for receiving the command transmitted by said memory update monitoring means to issue a write command, similar to that for said first computer, into a main memory of said second computer, wherein said first computer comprises: a plurality of processors and a system bus; a cache flush apparatus comprising: update address storage means having a plurality of regions provided to correspond to cache blocks provided in said cache memory for storing an address of data stored in a dirty block, each region having one entry and one counter; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data, storing the memory address MU as an update address in one of the entries of the selected region, and incrementing said counter corresponding to the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back, and decrementing said counter corresponding to the selected region; and flush executing means, in response to a request from any of said processors, for issuing, to said system bus, a command for sequentially reading update addresses stored in regions among the regions of said update address storage means of which count value is not an initial value, and writing-back into said main memory data of the dirty block indicated by the update address read; normal data processing means for performing normal data processing while causing said cache flush apparatus to acquire an update address; and checkpoint acquisition means including means for storing into said main memory the context of a data process which is synchronously performed and writing-back, into said main memory, data stored in all of the dirty blocks performed by said flush executing means of said cache flush apparatus, and issuing a command for transmitting the stored commands to said second computer; and said second computer comprises waiting means for starting the normal data processing when said memory update means does not receive a command from said memory update monitoring means.

Claim 66

A computer system having at least first and second computers and arranged to periodically extract a checkpoint for restarting an interrupted process, the system comprising: memory update monitoring means for acquiring a write command generated in said first computer, storing the write command to a main memory and transmitting a stored command to said second computer when it is instructed by said first computer; and memory update means for receiving the command transmitted by said memory update monitoring means to issue a write command, similar to that for said first computer, into a main memory of said second computer, wherein said first computer comprises: a plurality of processors and a system bus; a cache flush apparatus comprising: update address storage means having a plurality of regions provided to correspond to cache blocks provided in said cache memory for storing an address of data stored in a dirty block, each region having one entry and one counter; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data, storing the memory address MU as an update address in one of the entries of the selected region, and incrementing said counter corresponding to the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back, and decrementing said counter corresponding to the selected region; and flush executing means, in response to a request from any of said processors, for issuing, to said system bus, a command for sequentially reading update addresses stored in regions among the regions of said update address storage means of which count value is not an initial value, and writing-back into said main memory data of the dirty block indicated by the update address read; normal data processing means for performing normal data processing while causing said cache flush apparatus to acquire an update address; and checkpoint acquisition means including means for storing into said main memory the context of a data process which is synchronously performed and writing-back, into said main memory, data stored in all of the dirty blocks performed by said flush executing means of said cache flush apparatus, and issuing a command for transmitting the stored commands to said second computer; and said second computer comprises waiting means for starting the normal data processing when said memory update means does not receive a command from said memory update monitoring means.

Claim 67

A computer system having at least first and second computers and arranged to periodically extract a checkpoint for restarting an interrupted process, the system comprising: memory update monitoring means for acquiring a write command generated in said first computer, storing the write command to a main memory and transmitting a stored command to said second computer when it is instructed by said first computer; and memory update means for receiving the command transmitted by said memory update monitoring means to issue a write command, similar to that for said first computer, into a main memory of said second computer, wherein said first computer comprises: a plurality of processors and a system bus; a cache flush apparatus comprising: update address storage means having a plurality of regions each of which has one or more entries for storing the addresses of data held in dirty blocks; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data and storing the memory address MU as an update address in one of the entries of the selected region; entry reclaiming means for comparing the number of the empty entries of the region selected by said update address registering means with a predetermined value, selecting a stuffed entry of the selected region if the number of the empty entries is smaller than the predetermined value, issuing a bus command which causes a write-back of data stored in the cache block designated by the update address held in the selected entry, and changing the state of the selected entry from “stuffed” to “empty”; and flush executing means, in response to a request from any of said processors, for issuing bus commands to said system bus each of which has one of the update addresses stored in said update address storage means and causes a write-back of data from the dirty block designated by the update address; normal data processing means for performing normal data processing while causing said cache flush apparatus to acquire an update address; and checkpoint acquisition means including means for storing into said main memory the context of a data process which is synchronously performed by said processors and writing-back, into said main memory, data stored in all of the dirty blocks performed by said flush executing means of said cache flush apparatus, and issuing a command for transmitting the stored commands to said second computer; and said second computer comprises waiting means for starting the normal data processing when said memory update means does not receive a command from said memory update monitoring means.

Claim 68

A computer system according to claim 51 , in which said cache memory is an n-way set-associative type memory, and said plural regions of said update address storage means are provided to, one-to-one, correspond to groups each of which is formed by n cache blocks.

Claim 69

A computer system according to claim 51 , in which the number of entries of each of the plural regions of said update address storage means is smaller than the number of the corresponding cache blocks.

Claim 70

A computer system according to claim 51 , in which the plural regions of said update address storage means can be selected by the update address.

Claim 71

A computer system according to claim 51 , in which said update address storage means comprises a dirty block counter for storing a number of dirty blocks corresponding to the regions storing an address of data which is stored as a dirty block; and said update address registering means comprises means for incrementing said dirty block counter corresponding to the selected region, and characterized by further comprising: decrement means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to the memory address MW at which the data has been written back and the identifier of the processor from which the date has been written back, and decrementing the dirty block counter of the selected region; and entry reclaiming means, when the value of a dirty block counter is made to an initial value as a result of a decrement performed by said decrement means, for making all the entries of the selected region empty.

Claim 72

A computer system according to claim 55 , in which said entry reclaiming means, when the number of the update addresses stored in one of the plural regions of said update address storage means is larger than the count value of said dirty block counter corresponding to the region, selects one of the update addresses already stored in the region, issues a command for write-back of data stored in the dirty block indicated by the selected update address into said main memory, and makes the entry in which the update address is stored to be an empty entry.

Claim 73

A computer system having at least first and second computers and arranged to periodically extract a checkpoint for restarting an interrupted process, the system comprising: memory update monitoring means for acquiring a write command generated in said first computer, storing the write command to a main memory and transmitting a stored command to said second computer when it is instructed by said first computer; and memory update means for receiving the command transmitted by said memory update monitoring means to issue a write command, similar to that for said first computer, into a main memory of said second computer, wherein said first computer comprises: a plurality of processors and a system bus; a cache flush apparatus comprising: update address storage means having a plurality of regions each of which has one or more entries for storing the addresses of data held in dirty blocks; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data, and storing the memory address MU as an update address in one of the entries of the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back, detecting, for a predetermined time, whether or. not an update address which coincides with the write-back address exists in the selected region, and removing the update address which coincides with the write-back address; entry reclaiming means for comparing the number of the empty entries of the region selected by said update address registering means with a predetermined value, selecting a stuffed entry of the selected region if the number of the empty entries is smaller than the predetermined value, issuing a bus command which causes a write-back of data stored in the cache block designated by the update address held in the selected entry, and changing the state of the selected entry from “stuffed” to “empty”; and flush executing means, in response to a request from any of said processors, for issuing bus commands to said system bus each of which has one of the update addresses stored in said update address storage means and causes a write-back of data from the dirty block designated by the update address; normal data processing means for performing normal data processing while causing said cache flush apparatus to acquire an update address; and checkpoint acquisition means including means for storing into said main memory the context of a data process which is synchronously performed by said processors and writing-back, into said main memory, data stored in all of the dirty blocks performed by said flush executing means of said cache flush apparatus, and issuing a command for transmitting the stored commands to said second computer; and said second computer comprises waiting means for starting the normal data processing when said memory update means does not receive a command from said memory update monitoring means.

Claim 74

A cache flush apparatus according to claim 57 , in which said update address removing means, upon detecting that a cache block storing data of a given address is not a dirty block, selects one of the plural regions of said update address storage means based on the given address and, when it detects an update command coincides with the update address in the selected region, removes the update address.

Claim 75

A computer system according to claim 57 , in which the number of entries of each of the plural regions of said update address storage means is smaller than the number of the corresponding cache blocks.

Claim 76

A computer system according to claim 57 , in which the plural regions of said update address storage means can be selected by the update address.

Claim 77

A computer system according to claim 57 , in which said update address storage means comprises a dirty block counter for storing a number of dirty blocks corresponding to the regions storing an address of data which is stored as a dirty block; said update address registering means comprises means for incrementing said dirty block counter corresponding to the selected region; said update address removing means comprises means for decrementing said dirty block counter corresponding to the selected region, and characterized by further comprising: removing means for removing all of the update addresses stored in the region corresponding to said dirty block counter when said dirty block counter is made to be an initial value as a result of a decrement performed by said decrement means.

Claim 78

A computer system having at least first and second computers and arranged to periodically extract a checkpoint for restarting an interrupted process, the system comprising: memory update monitoring means for acquiring a write command generated in said first computer, storing the write command to a main memory and transmitting a stored command to said second computer when it is instructed by said first computer; and memory update means for receiving the command transmitted by said memory update monitoring means to issue a write command, similar to that for said first computer, into a main memory of said second computer, wherein said first computer comprises: a plurality of processors and a system bus; a cache flush apparatus comprising: update address storage means having a plurality of regions each of which has one or more entries for storing the addresses of data held in dirty blocks; update address registering means for monitoring said system bus to detect an update of data within said cache memory, selecting a region of said update address storage means according to a memory address MU at which the data has been updated and an identifier of a processor which has updated the data, and storing the memory address MU as an update address in one of the entries of the selected region; update address removing means for monitoring said system bus to detect a write-back of data from a dirty block into said main memory, selecting a region of said update address storage means according to a memory address MW at which the data has been written back and an identifier of a processor from which the data has been written back, determining whether or not an update address which coincides with the write-back address exists in the selected region until said cache flush apparatus detects a command which must be processed next, and removing the update address when an update address which coincides with the write-back address is detected; entry reclaiming means for comparing a number of empty entries of the region selected by said update address registering means with a predetermined value, selecting a stuffed entry of the selected region if the number of the empty entries is smaller than the predetermined value, issuing a bus command which causes a write-back of data stored in the cache block designated by the update address held in the selected entry, and changing the state of the selected entry from “stuffed” to “empty”; and flush executing means, in response to a request from any of said processors, for issuing bus commands to said system bus each of which has one of the update addresses stored in said update address storage means and causes a write-back of data from the dirty block designated by the update address; normal data processing means for performing normal data processing while causing said cache flush apparatus to acquire an update address; checkpoint acquisition means including means for storing into said main memory the context of a data process which is synchronously performed by said processors and writing-back, into said main memory, data stored in all of the dirty blocks performed by said flush executing means of said cache flush apparatus, and issuing a command for transmitting the stored commands to said second computer; and said second computer comprises waiting means for starting the normal data processing when said memory update means does not receive a command from said memory update monitoring means.

Claim 79

A computer system according to claim 62 , in which when said update address removing means detects a command indicating that all cache blocks for storing data indicated by a certain address are not dirty blocks, said update address removing means selects one of the plural regions of said update address storage means in accordance with the certain address, retrieves the selected region, and removes the update address when an update address which coincides with the write-back address is detected.

Claim 80

A computer system according to claim 62 , in which the number of entries of each of the plural regions of said update address storage means is smaller than the number of the corresponding cache blocks.

Claim 81

A computer system according to claim 62 , in which the plural regions of said update address storage means can be selected by the update address.

Claim 82

A computer system according to claim 62 , in which said update address storage means comprises a dirty block counter for storing the number of the dirty blocks corresponding to the regions storing an address of data which is stored by the dirty block; said update address registering means comprises means for incrementing said dirty block counter corresponding to the selected regions; said update address removing means comprises means for decrementing said dirty block counter corresponding to the selected region, and characterized by further comprising: removing means for removing all of the update addresses stored in the region corresponding to said dirty block counter when said dirty block counter is made to be an initial value as a result of a decrement performed by said decrement means.

Claim 83

A computer system according to one of claims 24 to 45 , and 47 to 66 , in which said normal data processing means includes a process for turning on said flush executing means of said cache flush apparatus.