EP0328172A1
Expired / Lapsed
EP
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Computer system comprising a hierarchically organized memory
Assignee: Digital Equipment Corp
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Filing: 1989-01-19
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Granted: —
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Expires: 2009-01-19
Abstract
Abstract A computer system includes a processor which is provided with a foreground memory or cache (fig. 2). The memory parts thereof have a validity bit (V) and a modification bit (D). When a modification occurs in the information of such a memory location, the modification bit is set to "modified" and the address of this memory location is stored in the registration memory (fig. 3). Copying to the main memory is necessary only when the registration memory has registered the relevant memory location. Ousting or flushing in the foreground memory is thus quickly effected. Each memory part in the foreground memory preferably comprises a signal bit (R) which indicates that the registration has taken place.
Inventors
- 👤 Fredericus Henricus Joseph Feldbrugge
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 22:46
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0804
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
182 words
A computer system, comprising as sub-systems a processor with a foreground memory, and a main memory, and a communication network interconnecting said sub-systems, the foreground memory having a plurality of memory parts, and being suitable for temporarily storing at least one information block from the main memory for priviliged use by the processor, for each memory part in the foreground memory there being provided a validity bit (valid) in order to indicate valid information storage therein and a modification bit (dirty) in order to indicate a modification effected therein, wherein there is provided a registration memory which comprises a row of further memory locations in which write operations can be performed in a predetermined first address sequence and which can be directly read thereafter in a predetermined second address sequence in order to store in each of said further memory locations each time the address of a memory part for which a said modification has taken place, and wherein of said memory parts there is provided a registration bit to indicate that the associated address has been stored in the registration memory.
Claim 2
Dependent Claim
182 words
A computer system, comprising as sub-systems a processor with a foreground memory, and a main memory, and a communication network interconnecting said sub-systems, the foreground memory having a plurality of memory parts, and being suitable for temporarily storing at least one information block from the main memory for priviliged use by the processor, for each memory part in the foreground memory there being provided a validity bit (valid) in order to indicate valid information storage therein and a modification bit (dirty) in order to indicate a modification effected therein, wherein there is provided a registration memory which comprises a row of further memory locations in which write operations can be performed in a predetermined first address sequence and which can be directly read thereafter in a predetermined second address sequence in order to store in each of said further memory locations each time the address of a memory part for which a said modification has taken place, and wherein of said memory parts there is provided a registration bit to indicate that the associated address has been stored in the registration memory.
Claim 3
Dependent Claim
26 words
A computer system as claimed in Claim 1, characterized in that all addresses of the memory parts can be stored exactly once in the registration memory.
Claim 4
Dependent Claim
29 words
A computer system as claimed in Claim 1 or 2, characterized in that the first address sequence and the second address sequence are always interrelated in the same way.
Claim 5
Dependent Claim
27 words
A computer system as claimed in Claim 1, 2 or 3, wherein upon ousting the content of a memory part, the associated registration bit is left unchanged.
References Cited (Backward Citations)
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