Hierarchial memory/storage system for an electronic computer

Claim 1

In a hierarchial memory system for use with an electronic computer system wherein said memory system includes a large capacity relatively low speed backing memory store, a plurality of bUffer memories located at different levels having increasingly smaller capacities and increasingly higher accessing speeds, the buffer memory at the lowest level responsive to a central processing unit, a plurality of buffer memory control means associated wih said buffer memories that coact and control the respective associated buffer memory that include first transferring means to transfer complete, but of variously defined sizes, pages of data from the backing memory store forward between the said buffer memories, mapping store means associated with each buffer memory to store and, upon inquiry, to indicate the identity and physical location of altered and unaltered page segments of data within said buffer memories, marker means in the said mapping store means to indicate altered page segments, the improvement comprising means to interrogate said mapping store means in response to a command from the central processing unit and/or one of the individual buffer memories, means to indicate buffer memories at upper levels when the requested data is not found in a buffer memory at a certain level, means to determine that a certain positive responding buffer memory at a specific level to the address search command is the buffer memory at the lowest positive responding level, means to form a path of expendable pages which are stored in the individual buffer memories between at least the buffer memory at the lowest level containing a data segment called for by the processing unit and the buffer memory at the level responding directly to the processing unit, and means to initiate said first transfer means to move a data page containing a requested data segment through said path.