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US6484295B1
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US
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Electrical rules checker system and method providing quality assurance of tri-state logic
Assignee: HP Inc
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Filing: 2000-08-15
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Granted: 2002-11-19
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Expires: 2020-08-15
Abstract
Abstract An electrical rules checker system and method are provided to appraise tri-state logic connected to a selected node of an integrated circuit by evaluating a netlist. In accordance with one aspect of the invention, the method selects a circuit configuration to be identified. Next, the method identifies any of the circuit configurations at the node, and identifies any probable circuit configurations at the node. Then the method appraises the circuit configurations and the probable circuit configurations. In accordance with another aspect of the invention, a system is provided for appraising tri-state logic connected to a selected node of an integrated circuit. The system operates by evaluating a netlist at the node, and further includes a code segment for selecting a circuit configuration to be identified, a second code segment for identify any of the selected circuit configurations a given node in a netlist, and a third code segment configured to identify any probable circuit configurations at the node in a netlist. A fourth code segment appraises the identified circuit configurations and probable circuit configurations.
Inventors
- 👤 John G McBride
- 👤 Jan Kok
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:41
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
60 words
A method for appraising tri-state logic connected to a selected node of an integrated circuit by evaluating a netlist at the node comprising the steps of: selecting a circuit configuration to be identified; identifying any of said circuit configurations at the node; identifying any probable circuit configurations at the node; and appraising said circuit configurations and said probable circuit configurations.
Claim 2
Independent Claim
60 words
A method for appraising tri-state logic connected to a selected node of an integrated circuit by evaluating a netlist at the node comprising the steps of: selecting a circuit configuration to be identified; identifying any of said circuit configurations at the node; identifying any probable circuit configurations at the node; and appraising said circuit configurations and said probable circuit configurations.
Claim 3
Dependent Claim
32 words
The method as defined in claim 1 , wherein the step of appraising said circuit configurations and said probable circuit configurations further includes the step of: obtaining a circuit configuration query type.
Claim 4
Dependent Claim
36 words
The method as defined in claim 2 , wherein the step of appraising said identified circuit configurations and said probable circuit configurations further includes the step of: determining if a circuit configuration is not positively identified.
Claim 5
Dependent Claim
37 words
The method as defined in claim 3 , wherein the step of determining if a circuit configuration is not positively identified further includes the step of: determining if a non-positively identified circuit configuration is to be appraised.
Claim 6
Dependent Claim
49 words
The method as defined in claim 3 , wherein the wherein the step of appraising said identified circuit configurations and said probable circuit configurations further includes the step of: performing quality analysis on any said circuit configurations and said probable circuit configurations that match said circuit configuration query type.
Claim 7
Independent Claim
66 words
A system for appraising tri-state logic connected to a selected node of an integrated circuit by evaluating a netlist at the node comprising: means for selecting a circuit configuration to be identified; means for identifying any of said circuit configurations at the node; means for identifying any probable circuit configurations at the node; and means for appraising said identified circuit configurations and said probable circuit configurations.
Claim 8
Independent Claim
66 words
A system for appraising tri-state logic connected to a selected node of an integrated circuit by evaluating a netlist at the node comprising: means for selecting a circuit configuration to be identified; means for identifying any of said circuit configurations at the node; means for identifying any probable circuit configurations at the node; and means for appraising said identified circuit configurations and said probable circuit configurations.
Claim 9
Dependent Claim
17 words
The system of claim 6 , further comprising: a means for obtaining a circuit configuration query type.
Claim 10
Dependent Claim
20 words
The system of claim 7 , further comprising: a means for determining if a circuit configuration is not positively identified.
Claim 11
Dependent Claim
22 words
The system of claim 8 , further comprising: a means for determining if a non-positively identified circuit configuration is to be appraised.
Claim 12
Dependent Claim
31 words
The system of claim 8 , further comprising: a means for performing quality analysis on any said circuit configurations and said probable circuit configurations that match said circuit configuration query type.
Claim 13
Dependent Claim
93 words
A computer readable storage medium containing program for appraising tri-state logic connected to a selected node of an integrated circuit by evaluating a netlist at the node comprising: a first code segment configured to selecting a circuit configuration to be identified; a second code segment configured to identify any of said circuit a given node in a netlist; and a third code segment configured to identify any probable circuit configurations at the node in a netlist; and a fourth code segment configured to appraise said identified circuit configurations and said probable circuit configurations.
Claim 14
Dependent Claim
93 words
A computer readable storage medium containing program for appraising tri-state logic connected to a selected node of an integrated circuit by evaluating a netlist at the node comprising: a first code segment configured to selecting a circuit configuration to be identified; a second code segment configured to identify any of said circuit a given node in a netlist; and a third code segment configured to identify any probable circuit configurations at the node in a netlist; and a fourth code segment configured to appraise said identified circuit configurations and said probable circuit configurations.
Claim 15
Dependent Claim
22 words
The program code of claim 11 , wherein said fourth code segment is further configured to obtaining a circuit configuration query type.
Claim 16
Dependent Claim
25 words
The program code of claim 12 , wherein said fourth code segment is further configured to determine if a circuit configuration is not positively identified.
Claim 17
Dependent Claim
27 words
The program code of claim 13 , wherein said fourth code segment is further configured to determining if a non-positively identified circuit configuration is to be appraised.
Claim 18
Dependent Claim
36 words
The program code of claim 14 , wherein said fourth code segment is further configured to performing quality analysis on any said circuit configurations and said probable circuit configurations that match said circuit configuration query type.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-11-18 | 2006-05-20 | 2006-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-11-18 | 2010-05-20 | 2010-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-11-18 | 2014-05-20 | 2014-11-19 | $7700.00 | Window Closed / Lapsed |