US6308301B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
System and method for detecting multiplexers in a circuit design
Assignee: Samsung Electronics Co Ltd
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Filing: 1999-07-21
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Granted: 2001-10-23
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Expires: 2019-07-21
Abstract
Abstract The present invention is directed to a system and method for identifying multiplexers from a netlist. In accordance with one aspect of the invention, a method identifies multiplexers from a netlist by identifying both an input node and an output node of a pass gate. The method then identifies all FETs that are channel connected to the output node, and evaluates all FETs that are identified as being channel connected to the output node, to determine whether they are pass FETs. Finally, the method determines whether at least one of the identified pass FETs has an output that is the same node as the output node and an input that is not the same node as the input node. In accordance with another aspect of the invention, the method identifies a node in the netlist that is an output node of a first pass FET and identifies at least one other pass FET that has an output that is the same node as the output node. Finally, the method evaluates the at least one other pass FET to determine whether an input of that other at least one other pass FET is not the same node as an input node of the first pass FET.
Inventors
- 👤 John G McBride
- 👤 Jan Kok
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 23:42
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
99 words
A method for identifying a circuit configured as a multiplexer by evaluating a netlist comprising the steps of: identifying both an input node and an output node of a pass gate; identifying all FETs that are channel connected to the output node; evaluating all FETs that are identified as being channel connected to the output node, to determine whether they are pass FETs; and determining whether at least one of the identified pass FETs has an output that is the same node as the output node and an input that is not the same node as the input node.
Claim 2
Independent Claim
99 words
A method for identifying a circuit configured as a multiplexer by evaluating a netlist comprising the steps of: identifying both an input node and an output node of a pass gate; identifying all FETs that are channel connected to the output node; evaluating all FETs that are identified as being channel connected to the output node, to determine whether they are pass FETs; and determining whether at least one of the identified pass FETs has an output that is the same node as the output node and an input that is not the same node as the input node.
Claim 3
Dependent Claim
44 words
The method as defined in claim 1 , wherein the step of evaluating all FETs that are identified as being channel connected to the output node includes evaluating an item in a data structure that has been predetermined and stored in the data structure.
Claim 4
Dependent Claim
40 words
The method as defined in claim 1 , wherein the step of evaluating all FETs that are identified as being channel connected to the output node includes evaluating each FET to determine whether a direction of each has been set.
Claim 5
Dependent Claim
45 words
The method as defined in claim 1 , wherein the step of evaluating all FETs that are identified as being channel connected to the output node includes evaluating each FET to determine a second input node and a second output node of the each FET.
Claim 6
Dependent Claim
58 words
The method as defined in claim 4 , wherein the step of evaluating all FETs that are identified as being channel connected to the output node further includes the step of evaluating other elements that are channel connected to the second input node to identify at least one of the other elements that drives the second input node.
Claim 7
Dependent Claim
63 words
The method as defined in claim 1 , wherein the step of determining whether at least one of the identified pass FETs has an output that is the same node as the output node and an input that is not the same node as the input node, further includes the step of determining whether a direction flag of the pass FET is set.
Claim 8
Dependent Claim
29 words
The method as defined in claim 1 , further including the step of marking the output node in a data structure as being the output node of a multiplexer.
Claim 9
Dependent Claim
30 words
The method as defined in claim 7 , wherein the step of marking the output node in a data structure more specifically includes setting a bit in the data structure.
Claim 10
Dependent Claim
38 words
The method as defined in claim 1 , wherein the step of identifying an input node and an output node of a pass gate, further includes the step of determining whether a current element is a pass gate.
Claim 11
Dependent Claim
45 words
The method as defined in claim 1 , wherein the step of determining whether a current element is a pass gate includes determining whether the current element is an element selected from the group consisting of: a complementary pass FET, and a single pass FET.
Claim 12
Independent Claim
91 words
A method for identifying a circuit configured as a multiplexer by evaluating a netlist comprising the steps of: identifying a node in the netlist that is an output node of a first pass FET; identifying at least one other pass FET that has an output that is the same node as the output node; and evaluating the at least one other pass FET to determine whether an input of that other at least one other pass FET is not the same node as an input node of the first pass FET.
Claim 13
Independent Claim
91 words
A method for identifying a circuit configured as a multiplexer by evaluating a netlist comprising the steps of: identifying a node in the netlist that is an output node of a first pass FET; identifying at least one other pass FET that has an output that is the same node as the output node; and evaluating the at least one other pass FET to determine whether an input of that other at least one other pass FET is not the same node as an input node of the first pass FET.
Claim 14
Dependent Claim
37 words
The method as defined in claim 11 , wherein the step of evaluating at least one pass FET includes evaluating each FET to determine a second input node and a second output node of the each FET.
Claim 15
Dependent Claim
50 words
The method as defined in claim 12 , wherein the step of evaluating at least one pass FET further includes the step of evaluating other elements that are channel connected to the second input node to identify at least one of the other elements that drives the second input node.
Claim 16
Dependent Claim
29 words
The method as defined in claim 11 , further including the step of marking the output node in a data structure as being the output node of a multiplexer.
Claim 17
Dependent Claim
115 words
A computer readable medium containing program code for controlling a system to identify a circuit configured as a multiplexer by evaluating a netlist comprising: a first code segment configured to identify a node in the netlist that is an output node of a first pass FET; a second code segment configured to identify at least one other pass FET that has an output that is the same node as the output node; and a third code segment configured to evaluate the at least one other pass FET to determine whether an input of that other at least one other pass FET is not the same node as an input node of the first pass FET.
Claim 18
Dependent Claim
115 words
A computer readable medium containing program code for controlling a system to identify a circuit configured as a multiplexer by evaluating a netlist comprising: a first code segment configured to identify a node in the netlist that is an output node of a first pass FET; a second code segment configured to identify at least one other pass FET that has an output that is the same node as the output node; and a third code segment configured to evaluate the at least one other pass FET to determine whether an input of that other at least one other pass FET is not the same node as an input node of the first pass FET.
Claim 19
Dependent Claim
45 words
The computer readable medium as defined in claim 15 , wherein the segment configured to evaluate at least one pass FET further includes a segment configured to evaluate each FET to determine a second input node and a second output node of the each FET.
Claim 20
Dependent Claim
54 words
The computer readable medium as defined in claim 16 , wherein the segment configured to evaluate at least one pass FET further includes a segment configured to evaluate other elements that are channel connected to the second input node to identify at least one of the other elements that drives the second input node.
Claim 21
Dependent Claim
32 words
The computer readable medium as defined in claim 15 , further including a segment configured to mark the output node in a data structure as being the output node of a multiplexer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-10-22 | 2005-04-23 | 2005-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-10-22 | 2009-04-23 | 2009-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-10-22 | 2013-04-23 | 2013-10-23 | $7700.00 | Window Closed / Lapsed |