Patent US5412596A successfully refreshed from Google Patents.
US6480033B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device
Assignee: Socionext Inc
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Filing: 1999-05-25
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Granted: 2002-11-12
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Expires: 2019-05-25
Abstract
Abstract A semiconductor integrated circuit including a semiconductor device has a command decoder unit for decoding command signals synchronously with an external clock. An internal signal whose timing precedes the timing of the command decoder unit decoding the command signals is used to reset the command decoder unit. Preferably, a signal produced by a DLL is used as the internal signal. Consequently, a margin in timing of actuating the semiconductor device is expanded.
Inventors
- 👤 Naoharu Shinozaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 17:45
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C7/00; G11C7/10; G11C7/1078; G11C7/109; G11C7/22; H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104; H03K3/356113; H03K3/35613; H03K3/356139
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
93 words
A semiconductor integrated circuit comprising: a command decoder unit for decoding command signals; a command decoder control circuit outputting a control signal to said command decoder unit, said control signal resetting said command decoder unit before said command decoder unit decodes said command signals, and said control signal activating said command decoder unit after all of said command signals are input to said command decoder unit; and a command latch circuit for latching external command signals in response to a clock signal and for outputting said command signals to said command decoder unit.
Claim 2
Dependent Claim
93 words
A semiconductor integrated circuit comprising: a command decoder unit for decoding command signals; a command decoder control circuit outputting a control signal to said command decoder unit, said control signal resetting said command decoder unit before said command decoder unit decodes said command signals, and said control signal activating said command decoder unit after all of said command signals are input to said command decoder unit; and a command latch circuit for latching external command signals in response to a clock signal and for outputting said command signals to said command decoder unit.
Claim 3
Dependent Claim
27 words
The semiconductor integrated circuit according to claim 1 , wherein said control signal is generated in response to said clock signal to reset said command decoder unit.
Claim 4
Dependent Claim
47 words
The semiconductor integrated circuit according to claim 1 , further comprising: a dummy latch circuit for simulating an operation of said command latch circuit, wherein said control signal is generated in response to an output signal of said dummy latch circuit to activate said command decoder unit.
Claim 5
Dependent Claim
40 words
The semiconductor integrated circuit according to claim 1 , wherein in a reset state of said command decoder unit, an internal node of said command decoder unit is precharged to a power supply voltage in response to said control signal.
Claim 6
Dependent Claim
33 words
The semiconductor integrated circuit according to claim 4 , wherein during an activation period of said command decoder unit, said internal node is discharged or not discharged in response to said command signals.
Claim 7
Dependent Claim
45 words
The semiconductor integrated circuit according to claim 1 , further comprising: a DLL circuit receiving said clock signal for outputting a controlled clock signal in phase, wherein said control signal is generated in response to said controlled clock signal to reset said command decoder unit.
Claim 8
Dependent Claim
80 words
A semiconductor integrated circuit according to claim 1 , said command decoder unit comprising: a first, second and third PMOS transistors coupled in parallel between a power supply voltage and an internal node, and a gate of said first PMOS transistor being controlled by said control signal, gates of said second and third PMOS transistors are controlled by said command signals respectively; and first, second and third NMOS transistors coupled in series between said internal node and a reference potential.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-11-11 | 2006-05-13 | 2006-11-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-11-11 | 2010-05-13 | 2010-11-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-11-11 | 2014-05-13 | 2014-11-12 | $7700.00 | Window Closed / Lapsed |