Synchronous semiconductor memory device having internal circuitry enabled only when commands are applied in normal sequence

Claim 2

A synchronous semiconductor memory device operating in synchronization with an externally, periodically and repetitively applied clock signal, comprising: a first command decoder for determining states of a plurality of external control signals applied externally in synchronization with said clock signal, and generating an activating signal activating a predetermined first internal operation when a first combination of states of said external control signals is found; and a second command decoder enabled in response to the activating signal from said first command decoder to determine the states of said plurality of external control signals applied in synchronization with said clock signal and activate a second internal operation different from said first internal operation when a second combination of states of the external control signals different from said first combination of states is found.

Claim 3

The synchronous semiconductor memory device according to claim 1 further comprising a plurality of memory cells each storing information, wherein said first command decoder activates an operation of selecting memory cells in said plurality of memory cells, and said second command decoder activates an operation of externally inputting or outputting data into or from the selected of memory cells.

Claim 4

The synchronous semiconductor memory device according to claim 1, further comprising a plurality of memory cells each storing information, wherein said first command decoder activates an operation of selecting memory cells in said plurality of memory cells, and said second command decoder activates an operation of terminating the operation of selecting the memory cells.

Claim 5

The synchronous semiconductor memory device according to claim 1, further comprising a third command decoder enabled in response to an activating signals activating said second internal operation from said second command decoder to determine the states of said plurality of external control signals applied in synchronization with said clock signal and activate an operation of terminating said first internal operation when a third combination of states of said plurality of external control signals different from said first and second combinations of states is found.

Claim 6

The synchronous semiconductor memory device according to claim 1 further comprising a plurality of memory cells each storing information, wherein said first command decoder activates an access operation to the selected memory cells among said plurality of memory cells, and said second command decoder activates an operation of setting said plurality of memory cells to a standby state.

Claim 7

The synchronous semiconductor memory device according to claim 1 further comprising a plurality of banks each having a plurality of memory cells each storing information, memory select operations in said plurality of banks performed independently from each other, wherein said first and second command decoders are provided corresponding to each of said plurality of banks.

Claim 8

The synchronous semiconductor memory device according to claim 4 further comprising a plurality of banks each having a plurality of memory cells each storing information, memory select operations in said plurality of banks performed independently from each other, wherein sets of said first, second and third command decoders are provided corresponding to each of said plurality of banks.

Claim 9

A synchronous semiconductor memory device operating in synchronization with an externally, periodically and repetitively applied clock signal comprising: a plurality of memory cells each storing information; a first command decoder for determining states of a plurality of externally applied external signals in synchronization with said clock signal, and activating an operation of selecting said plurality of memory cells when a first combination of states of said plurality of external signals is found; a command register for storing data defining a operation form of said synchronous semiconductor memory device; and a second command decoder for determining the states of said plurality of external signals in synchronization with said clock signal, and, when a second combination of states of said plurality of external signals different from said first combination of states is found, operating to inhibit the determining operation of said first command decoder, deactivate the select operation for said plurality of memory cells and activate an operation mode for storing externally applied data defining the operation form to said command register.

Claim 10

A synchronous semiconductor memory device operating in synchronization with an externally, periodically and repetitively applied clock signal comprising: a plurality of memory cells each storing information; a first command decoder for determining states of a plurality of externally applied external signals in synchronization with said clock signal, and activating an operation of selecting said plurality of memory cells when a first combination of states of said plurality of external signals is found; a command register for storing data defining a operation form of said synchronous semiconductor memory device; and a second command decoder for determining the states of said plurality of external signals in synchronization with said clock signal, and, when a second combination of states of said plurality of external signals different from said first combination of states is found, operating to inhibit the determining operation of said first command decoder, deactivate the select operation for said plurality of memory cells and activate an operation mode for storing externally applied data defining the operation form to said command register.

Claim 11

A synchronous semiconductor memory device operating in synchronization with an externally, periodically and repetitively applied clock signal, comprising: a plurality of memory cells storing data a first command decoder for decoding a plurality of external control signals applied in synchronization with the clock signal to activate a refresh instruction signal instructing a refreshing operation of storage data in the memory cells in accordance with the result of decoding a refresh controller responsive to said refresh instruction signal for generating a refresh operation activation signal activating the refresh operation; a second command decoder enabled in response to said refresh operation activation signal, for decoding the external control signals to activate an active signal activating a memory cell selection operation in accordance with the result of decoding.

Claim 12

A synchronous semiconductor memory device operating in synchronization with an externally, periodically and repetitively applied clock signal, comprising: a plurality of memory cells storing data a first command decoder for decoding a plurality of external control signals applied in synchronization with the clock signal to activate a refresh instruction signal instructing a refreshing operation of storage data in the memory cells in accordance with the result of decoding a refresh controller responsive to said refresh instruction signal for generating a refresh operation activation signal activating the refresh operation; a second command decoder enabled in response to said refresh operation activation signal, for decoding the external control signals to activate an active signal activating a memory cell selection operation in accordance with the result of decoding.