Synchronous semiconductor memory device capable of improving load of clock signal line

Claim 2

A synchronous semiconductor memory device comprising: a memory cell array; means for generating an internal address signal in synchronization with an external clock signal; decoder means for reading out data from said memory cell array according to the internal address signal; internal clock generation means for generating an internal clock signal having a frequency equal to 1/2 of the frequency of said external clock signal in synchronization with said external clock signal; and data output means for outputting the data read out of said memory cell array in synchronization with both a rising edge and a falling edge of said internal clock signal.

Claim 3

A synchronous semiconductor memory device comprising: a plurality of switch lines; a read bus; a plurality of sense amplifiers, each connected to said read bus and one of said switch lines; a plurality of groups of memory cells, each group connected to one of said sense amplifiers; a data amplifier connected to said read bus; an output circuit connected to said data amplifier; a selection circuit, connected to said switch lines, for sequentially selecting said switch lines in synchronization with an external clock signal; an internal clock signal generation circuit for generating an internal clock signal having a frequency equal to 1/2 of the frequency of said external clock signal; and a data amplifier activation signal generation circuit, connected between said internal clock signal generation circuit and said data amplifier, for generating a data amplifier activation signal in synchronization with a rising edge and a falling edge of said internal clock signal and transmitting said data amplifier activation signal to said data amplifier.

Claim 4

A synchronous semiconductor memory device comprising: a plurality of switch lines; a read bus; a plurality of sense amplifiers, each connected to said read bus and one of said switch lines; a plurality of groups of memory cells, each group connected to one of said sense amplifiers; a data amplifier connected to said read bus; an output circuit connected to said data amplifier; a selection circuit, connected to said switch lines, for sequentially selecting said switch lines in synchronization with an external clock signal; an internal clock signal generation circuit for generating an internal clock signal having a frequency equal to 1/2 of the frequency of said external clock signal; and a data amplifier activation signal generation circuit, connected between said internal clock signal generation circuit and said data amplifier, for generating a data amplifier activation signal in synchronization with a rising edge and a falling edge of said internal clock signal and transmitting said data amplifier activation signal to said data amplifier.

Claim 5

The device as set forth in claim 2, wherein said internal clock signal generation circuit comprises a 1/2 frequency divider formed by a D-type flip-flop.

Claim 6

The device as set forth in claim 2, wherein said data amplifier activation signal generation circuit comprises: a circuit for delaying and inverting said internal clock signal; and an exclusive OR circuit for receiving said internal clock signal and a signal from said circuit and generating said data amplifier activation signal.

Claim 7

A synchronous semiconductor memory device comprising: a memory cell array divided into at least first and second blocks; means for generating an internal address signal in synchronization with an external clock signal; decoder means for reading out data from the first and second blocks of said memory cell array according to the internal address signal; internal clock generation means for generating an internal clock signal having a frequency equal to 1/2 of the frequency of said external clock signal in synchronization with the external clock signal; first data output means for outputting the data read out of the first block of said memory cell array in synchronization with one of a rising edge and a falling edge of said internal clock signal; and second data output means for outputting the data read out of the second block of said memory cell array in synchronization with the other of a rising edge and a falling edge of said internal clock signal.

Claim 8

A synchronous semiconductor memory device comprising: a memory cell array divided into at least first and second blocks; means for generating an internal address signal in synchronization with an external clock signal; decoder means for reading out data from the first and second blocks of said memory cell array according to the internal address signal; internal clock generation means for generating an internal clock signal having a frequency equal to 1/2 of the frequency of said external clock signal in synchronization with the external clock signal; first data output means for outputting the data read out of the first block of said memory cell array in synchronization with one of a rising edge and a falling edge of said internal clock signal; and second data output means for outputting the data read out of the second block of said memory cell array in synchronization with the other of a rising edge and a falling edge of said internal clock signal.

Claim 9

A synchronous semiconductor memory device comprising: a plurality of switch lines; first and second read buses; a plurality of sense amplifiers, each connected to one of said read buses and one of said switch lines; a plurality of groups of memory cells, each group connected to one of said sense amplifiers; first and second data amplifiers connected to said first and second read buses, respectively; an output circuit connected to said first and second data amplifiers; a selection circuit, connected to said switch lines, for sequentially selecting said switch lines in synchronization with an external clock signal; an internal clock signal generation circuit for generating an internal clock signal having a frequency equal to 1/2 of the frequency of said external clock signal; a first data amplifier activation signal generation circuit, connected between said internal clock signal generation circuit and said first data amplifier, for generating a first data amplifier activation signal in synchronization with a rising edge of said internal clock signal and transmitting said first data amplifier activation signal to said first data amplifier; and a second data amplifier activation signal generation circuit, connected between said internal clock signal generation circuit and said second data amplifier, for generating a second data amplifier activation signal in synchronization with a falling edge of said internal clock signal and transmitting said second data amplifier activation signal to said second data amplifier.

Claim 10

A synchronous semiconductor memory device comprising: a plurality of switch lines; first and second read buses; a plurality of sense amplifiers, each connected to one of said read buses and one of said switch lines; a plurality of groups of memory cells, each group connected to one of said sense amplifiers; first and second data amplifiers connected to said first and second read buses, respectively; an output circuit connected to said first and second data amplifiers; a selection circuit, connected to said switch lines, for sequentially selecting said switch lines in synchronization with an external clock signal; an internal clock signal generation circuit for generating an internal clock signal having a frequency equal to 1/2 of the frequency of said external clock signal; a first data amplifier activation signal generation circuit, connected between said internal clock signal generation circuit and said first data amplifier, for generating a first data amplifier activation signal in synchronization with a rising edge of said internal clock signal and transmitting said first data amplifier activation signal to said first data amplifier; and a second data amplifier activation signal generation circuit, connected between said internal clock signal generation circuit and said second data amplifier, for generating a second data amplifier activation signal in synchronization with a falling edge of said internal clock signal and transmitting said second data amplifier activation signal to said second data amplifier.

Claim 11

The device as set forth in claim 6, wherein said internal clock signal generation circuit comprises a 1/2 frequency divider formed by a D-type flip-flop.

Claim 12

The device as set forth in claim 6, wherein said first data amplifier activation signal generation circuit comprises: a first circuit for delaying and inverting said internal clock signal; and an AND circuit for receiving said internal clock signal and a signal from said first circuit and generating said first data amplifier activation signal, said second data amplifier activation signal generation circuit comprising: a second circuit for delaying and inverting said internal clock signal; and a NOR circuit for receiving said internal clock signal and a signal from said second circuit and generating said second data amplifier activation signal.