Differential output driver circuit and method for same

Claim 2

An output driver circuit comprising: a final stage differential amplifier including emitter-coupled first and second transistors, a pair of differential outputs, and a pair of differential inputs; a pre-driver stage differential amplifier including emitter-coupled first and second transistors and a pair of differential outputs connected to the differential inputs of the final stage differential amplifier; a cascode connected to the final stage differential amplifier to maintain a constant voltage at the collectors of the first and second transistors of the final stage differential amplifier; and a first and second load resistor, with the first load resistor first input operatively connected to a final stage differential amplifier first transistor collector through the cascode, and the second load resistor first input operatively connected to a final stage differential amplifier second transistor collector through the cascode; wherein the cascode includes a pair of cascoded transistors, with a first cascode transistor having a collector connected to the first load resistor first input and an emitter connected to the collector of the final stage differential amplifier first transistor, a second cascode transistor having a collector connected to the second load resistor first input and an emitter connected to the collector of the final stage differential amplifier second transistor, and wherein the cascode includes a first current bleeder connected to the collector of the final stage differential amplifier first transistor, and a second current bleeder connected to the collector of the final stage differential amplifier second transistor.

Claim 3

The circuit of claim 1 in which the pre-driver differential amplifier first transistor collector is connected to the base of the final stage differential amplifier second transistor, and the pre-driver differential amplifier second transistor collector is connected to the base of the final stage differential amplifier first transistor.

Claim 4

The circuit of claim 1 in which the cascode includes a bias circuit for the first and second cascode transistors comprising: a first bias transistor having an emitter connected to the bases of the first and second cascode transistors, a second bias transistor having a collector connected to the base of the first bias transistor, and a third bias transistor having a collector connected to the emitter of the first bias transistor and a base connected to the base of the second bias transistor.

Claim 5

The circuit of claim 3 in which the first current bleeder includes a first current bleeder transistor having a-collector connected to the collector of the final stage differential amplifier first transistor and a base connected to the base of the second bias transistor, and second current bleeder transistor having a collector connected to the collector of the final stage differential amplifier second transistor and a base connected to the base of the second bias transistor.

Claim 6

The circuit of claim 4 further comprising: a first constant current source transistor having a collector connected to the emitters of the final stage differential amplifier first and second transistors, and a base connected to the base of the second bias transistor; and a second constant current source transistor having a collector connected to the emitters of the pre-driver stage differential amplifier first and second transistors.

Claim 7

The circuit of claim 5 further comprising: a first reference voltage having a first voltage; a second reference voltage, having a second voltage less than the first voltage; a first bias resistor having a first input connected to the base of the first bias transistor and a second input connected to the first reference voltage; a second bias resistor having a first input connected to the emitter of the second bias transistor and a second input connected to the second reference voltage; a third bias resistor having a first input connected to the emitter of the third bias transistor and a second input connected to the second reference voltage; a first current bleeder resistor having a first input connected to the emitter of the first current bleeder transistor and a second input connected to the second reference voltage; a second current bleeder resistor having a first input connected to the emitter of the second current bleeder transistor and a second input connected to the second reference voltage; a first constant current resistor having a first input connected to the emitter of the first constant current source transistor and a second input connected to the second reference voltage; a second constant current resistor having a first input connected to the emitter of the second constant current source transistor and a second input connected to the second reference voltage; a tap resistor having a first input connected to the first reference voltage and a second input; a first collector resistor having a first input connected to the second input of the tap resistor, and a second input connected to the collector of the pre-driver stage differential amplifier first transistor; a second collector resistor having a first input connected to the second input of the tap resistor, and a second input connected to the collector of the pre-driver stage differential amplifier second transistor; in which the collector of the first bias transistor is connected to the first reference voltage; and in which the first and second load resistors have second inputs connected to the first reference voltage.

Claim 8

The circuit of claim 6 in which the final stage differential amplifier has a first differential output connected to the first input of the first load resistor; and in which the final stage differential amplifier has a second differential output connected to the first input of the first load resistor.

Claim 9

In a circuit having inputs, a method for amplifying differential signals, the method comprising: providing a final stage differential amplifier including an emitter-coupled transistor pair; providing a cascode including a pair of transistors cascoded with the final stage emitter-coupled transistors; receiving a pair of differential input signals at a corresponding pair of circuit inputs of the final stage differential amplifier including receiving a varying voltage input signal at each of the bases of the final stage emitter-coupled transistors; differentially amplifying the input signals; simultaneously with the amplification of the differential input signals, eliminating changes in the capacitance of the circuit inputs responsive to the amplification of the differential input signals, including eliminating the Miller-effect capacitance at the bases of the final stage emitter-coupled transistors as the differential input signals vary in voltage by, with the cascode transistor pair, maintaining a constant voltage at the collectors of the final stage emitter-coupled transistors and bleeding current from the collectors of the final stage emitter-coupled transistors; and providing a pair of differential output signals which are amplified replicas of the corresponding differential input signals.

Claim 10

In a circuit having inputs, a method for amplifying differential signals, the method comprising: providing a final stage differential amplifier including an emitter-coupled transistor pair; providing a cascode including a pair of transistors cascoded with the final stage emitter-coupled transistors; receiving a pair of differential input signals at a corresponding pair of circuit inputs of the final stage differential amplifier including receiving a varying voltage input signal at each of the bases of the final stage emitter-coupled transistors; differentially amplifying the input signals; simultaneously with the amplification of the differential input signals, eliminating changes in the capacitance of the circuit inputs responsive to the amplification of the differential input signals, including eliminating the Miller-effect capacitance at the bases of the final stage emitter-coupled transistors as the differential input signals vary in voltage by, with the cascode transistor pair, maintaining a constant voltage at the collectors of the final stage emitter-coupled transistors and bleeding current from the collectors of the final stage emitter-coupled transistors; and providing a pair of differential output signals which are amplified replicas of the corresponding differential input signals.

Claim 11

The method of claim 8 wherein a pre-driver stage differential amplifier including a pair of emitter-coupled transistors is provided, and further comprising: providing the differential output signal from corresponding collectors of the pre-driver differential amplifier emitter-coupled transistors.

Claim 12

An output driver circuit comprising: a final stage means for differentially amplifying a pair of input signals to generate a pair of output signals; a pre-driver stage means for differentially amplifying a pair of pre-driver input signals, to provide the input signals to the final stage differential amplifying means; a means for generating an output impedance of the final stage amplifying means; and a means for buffering the output signals of the final stage differential amplifying means from changes to the input signals from the output impedance of the final stage amplifying means; in which the final stage differential amplifying means includes a first and second emitter-coupled transistor; in which the output impedance means includes a first and second load resistor; in which the buffering means includes a pair of cascoded transistors, with a first cascode transistor having a collector connected to the first load resistor and an emitter connected to the collector of the final stage differential amplifier first transistor, and a second cascode transistor having a collector connected to the second load resistor and an emitter connected to the collector of the final stage differential amplifier second transistor; and in which the buffering means includes a first means for bleeding current connected to the collector of the final stage first transistor, and a second means for bleeding current connected to toe collector of the final stage second transistor.

Claim 13

An output driver circuit comprising: a final stage means for differentially amplifying a pair of input signals to generate a pair of output signals; a pre-driver stage means for differentially amplifying a pair of pre-driver input signals, to provide the input signals to the final stage differential amplifying means; a means for generating an output impedance of the final stage amplifying means; and a means for buffering the output signals of the final stage differential amplifying means from changes to the input signals from the output impedance of the final stage amplifying means; in which the final stage differential amplifying means includes a first and second emitter-coupled transistor; in which the output impedance means includes a first and second load resistor; in which the buffering means includes a pair of cascoded transistors, with a first cascode transistor having a collector connected to the first load resistor and an emitter connected to the collector of the final stage differential amplifier first transistor, and a second cascode transistor having a collector connected to the second load resistor and an emitter connected to the collector of the final stage differential amplifier second transistor; and in which the buffering means includes a first means for bleeding current connected to the collector of the final stage first transistor, and a second means for bleeding current connected to toe collector of the final stage second transistor.

Claim 14

The circuit of claim 10 in which the pre-driver stage means includes a first transistor with a collector connected to the base of the final stage second transistor, and a second transistor with a collector connected to the base of the final stage first transistor.

Claim 15

The circuit of claim 10 in which the first current bleeding means includes a first current bleeder transistor having a collector connected to the collector of the final stage first transistor and second current bleeder transistor having a collector connected to the collector of the final stage second transistor.

Claim 16

An output driver circuit comprising: a final stage differential amplifier including emitter-coupled first and second transistors, a pair of differential outputs, and a pair of differential inputs; a pre-driver stage differential amplifier including emitter-coupled first and second transistors and a pair of differential outputs connected to the differential inputs of the final stage differential amplifier; a cascode including a pair of cascoded transistors connected to the final stage differential amplifier; and a first and second load resistor, the first load resistor having a first input connected to a final stage differential amplifier first transistor collector through the cascode, and the second load resistor having a first input connected to a final stage differential amplifier second transistor collector through the cascode; wherein a first cascode transistor has a collector connected to the first load resistor first input and an emitter connected to the collector of the final stage differential amplifier first transistor, a second cascode transistor has a collector connected to the second load resistor first input and an emitter connected to the collector of the final stage differential amplifier second transistor, and wherein the cascode includes a first current bleeder connected to the collector of the final stage differential amplifier first transistor, and a second current bleeder connected to the collector of the final stage differential amplifier second transistor.

Claim 17

An output driver circuit comprising: a final stage differential amplifier including emitter-coupled first and second transistors, a pair of differential outputs, and a pair of differential inputs; a pre-driver stage differential amplifier including emitter-coupled first and second transistors and a pair of differential outputs connected to the differential inputs of the final stage differential amplifier; a cascode including a pair of cascoded transistors connected to the final stage differential amplifier; and a first and second load resistor, the first load resistor having a first input connected to a final stage differential amplifier first transistor collector through the cascode, and the second load resistor having a first input connected to a final stage differential amplifier second transistor collector through the cascode; wherein a first cascode transistor has a collector connected to the first load resistor first input and an emitter connected to the collector of the final stage differential amplifier first transistor, a second cascode transistor has a collector connected to the second load resistor first input and an emitter connected to the collector of the final stage differential amplifier second transistor, and wherein the cascode includes a first current bleeder connected to the collector of the final stage differential amplifier first transistor, and a second current bleeder connected to the collector of the final stage differential amplifier second transistor.