High speed current mode logic circuit with constant logic level current

Claim 2

A collector-dotted current-mode logic circuit comprising: a first current-mode logic circuit section which includes first and second transistors with their respective emitters commonly connected, a first load resistor and a clamping diode connected in parallel between the collector of said first transistor and a first voltage terminal, a second load resistor connected between the collector of said second transistor and said first voltage terminal, and a first constant current source connected between the emitters of said first and second transistors and a second voltage terminal; a second current-mode logic circuit section which includes third and fourth transistors with the respective emitters commonly connected, and a second constant current source connected between the emitters of said third and fourth transistors and said second voltage terminal, the collector of said third transistor being connected to the collector of said first transistor, said first load resistor and said clamping diode, the collector of said fourth transistor being connected to the collector of said second transistor and said second load resistor; means for bypassing the current from one of said first and second constant current sources to prevent it from flowing through said second load resistor when both of said second and fourth transistors are in a conductive state; a first input terminal connected to the base of said first transistor; a second input terminal connected to the base of said third transistor; a reference voltage terminal connected to the bases of said second and fourth transistors; and a means for generating an output signal based on a voltage drop across said second load resistance.

Claim 3

A collector-dotted current-mode logic circuit as claimed in claim 1, wherein said maintaining means comprises: a fifth transistor with its collector connected to said first voltage terminal and its emitter connected to the emitter of said fourth transistor; and means for transmitting the collector potential of said third transistor to the base of said fifth transistor.

Claim 4

A collector-dotted current-mode logic circuit comprising: a first current-mode logic circuit section which includes first and second transistors with the respective emitters commonly connected, a first load resistor and a clamping diode connected in parallel between the collector of said first transistor and a first voltage terminal, a second load resistor connected between the collector of said second transistor and said first voltage terminal, and a first constant current source connected between the emitters of said first and second transistors and a second voltage terminal of said power supply; a second current-mode logic circuit section which includes a third and a fourth transistors with the respective emitters commonly connected, and a second constant current source connected between the emitters of said third and fourth transistors and said second voltage terminal, the collector of said third transistor being connected to the collector of said fourth transistor and the collector of said fourth transistor being connected to the collector of said second transistor; means for applying a reference potential to at least one of said second and fourth transistors; a fifth transistor with its collector connected to said first voltage terminal with its base connected directly or via an emitter follower circuit to the collector of said first transistor, and its emitter connected to the emitter of said second or fourth transistor to which is applied said reference potential; and a logic output terminal connected to a junction of said second load resistor and the collectors of said seocnd and fourth transistors.

Claim 5

A collector-dotted current-mode logic circuit comprising: a first current-mode logic circuit section which includes first and second transistors with the respective emitters commonly connected, a first load resistor and a clamping diode connected in parallel between the collector of said first transistor and a first voltage terminal, a second load resistor connected between the collector of said second transistor and said first voltage terminal, and a first constant current source connected between the emitters of said first and second transistors and a second voltage terminal of said power supply; a second current-mode logic circuit section which includes a third and a fourth transistors with the respective emitters commonly connected, and a second constant current source connected between the emitters of said third and fourth transistors and said second voltage terminal, the collector of said third transistor being connected to the collector of said fourth transistor and the collector of said fourth transistor being connected to the collector of said second transistor; means for applying a reference potential to at least one of said second and fourth transistors; a fifth transistor with its collector connected to said first voltage terminal with its base connected directly or via an emitter follower circuit to the collector of said first transistor, and its emitter connected to the emitter of said second or fourth transistor to which is applied said reference potential; and a logic output terminal connected to a junction of said second load resistor and the collectors of said seocnd and fourth transistors.

Claim 6

A collector-dotted current-mode circuit comprising: a first current-mode logic circuit section which includes a first and a second transistors with their respective emitters commonly connected, a first load resistor connected between the collector of said first transistor and a first voltage terminal, a second load resistor and a clamping diode connected in parallel between the collector of said second transistor and said first voltage terminal, and a first constant current source connected between the emitters of said first and second transistors and a second voltage terminal; a second current-mode logic circuit section which includes a plurality of current-mode logic circuits, each of these circuits having a third, a fourth and a fifth transistor with their respective emitters commonly connected, a logic signal input terminal connected to the base of said third transistor, a reference potential application terminal connected to the base of said fifth transistor, with the collector of said fourth transistor being connected to the first voltage terminal, a two terminal switching circuit having one of its terminals connected to said commonly connected emitters of said third, fourth and fifth transistors of each of the current-mode logic circuit and the other of its terminals commonly connected, and a second constant current source connected between said switching circuit and said second voltage terminal, the collectors of said third transistors of said plurality of current-mode logic circuits being connected to the collector of said second transistor, the bases of said fourth transistors being connected to the collector of said second transistor via an emitter follower circuit, and the collectors of said fifth transistors being connected to the collector of said first transistor; and means for selecting one of said plurality of current-mode logic circuits of said second current-mode logic circuit section by controlling said switching circuit and setting it at the on-state; whereby the low level at the collector of said second transistor is maintained constant regardless of the input level of the logic signals input to said first current-mode logic circuit part and said selected CML circuit.

Claim 7

A collector-dotted current-mode circuit comprising: a first current-mode logic circuit section which includes a first and a second transistors with their respective emitters commonly connected, a first load resistor connected between the collector of said first transistor and a first voltage terminal, a second load resistor and a clamping diode connected in parallel between the collector of said second transistor and said first voltage terminal, and a first constant current source connected between the emitters of said first and second transistors and a second voltage terminal; a second current-mode logic circuit section which includes a plurality of current-mode logic circuits, each of these circuits having a third, a fourth and a fifth transistor with their respective emitters commonly connected, a logic signal input terminal connected to the base of said third transistor, a reference potential application terminal connected to the base of said fifth transistor, with the collector of said fourth transistor being connected to the first voltage terminal, a two terminal switching circuit having one of its terminals connected to said commonly connected emitters of said third, fourth and fifth transistors of each of the current-mode logic circuit and the other of its terminals commonly connected, and a second constant current source connected between said switching circuit and said second voltage terminal, the collectors of said third transistors of said plurality of current-mode logic circuits being connected to the collector of said second transistor, the bases of said fourth transistors being connected to the collector of said second transistor via an emitter follower circuit, and the collectors of said fifth transistors being connected to the collector of said first transistor; and means for selecting one of said plurality of current-mode logic circuits of said second current-mode logic circuit section by controlling said switching circuit and setting it at the on-state; whereby the low level at the collector of said second transistor is maintained constant regardless of the input level of the logic signals input to said first current-mode logic circuit part and said selected CML circuit.

Claim 8

An AND gate circuit with an enable signal terminal comprising: a first current-mode logic circuit section which includes a first and a second transistor with their respective emitters commonly connected, a first load resistor connected between the collector of said first transistor and a first voltage terminal, a second load resistor and a clamping diode connected in parallel between the collector of said second transistor and said first voltage terminal, and a first constant current source connected between the emitters of said first and second transistors and said second voltage terminal; a second current-mode logic circuit section which includes a third, a fourth and a fifth transistor with their respective emitters commonly connected, a sixth transistor with its collector connected to the emitters of said third, fourth and fifth transistors, a first logic signal input terminal connected to the base of said third transistor, and a first reference potential application terminal connected to the base of said fifth transistor, the collector of said third transistor being connected to the collector of said second transistor, the collector of said fourth transistor being connected to said first voltage terminal and its base being connected to the collector of said second transistor via an emitter follower, and the collector of said fifth transistor being connected to the collector of said first transistor; a third current-mode logic circuit section which includes a seventh, an eighth and a ninth transistor with their respective emitters commonly connected, a tenth transistor with its collector connected to the emitters of said seventh, eighth and ninth transistors, a second logic signal input terminal connected to the base of said seventh transistor, and a second reference potential application terminal connected to the base of said tenth transistor, the collector of said seventh transistor being connected to the collector of said third transistor, the collector of said eighth transistor being connected to said first voltage terminal and its base being connected to the base of said fourth transistor, and the collector of said ninth transistor being connected to the collector of said fifth transistor and its base being connected to said first reference potential application terminal; a second constant current source connected between the emitters of said sixth and tenth transistors and said second voltage terminal which is shared by said second and third current-mode logic circuit parts; a selection circuit section which includes an eleventh transistor that has its collector connected to the first voltage terminal, its emitter being connected to the base of said transistor and also to said second voltage terminal via a resistor, and a selection terminal connected to the base of said eleventh transistor; and a logic output terminal connected via an emitter-follower to a junction of collectors of said first, fifth and ninth transistors.

Claim 9

An AND gate circuit with an enable signal terminal comprising: a first current-mode logic circuit section which includes a first and a second transistor with their respective emitters commonly connected, a first load resistor connected between the collector of said first transistor and a first voltage terminal, a second load resistor and a clamping diode connected in parallel between the collector of said second transistor and said first voltage terminal, and a first constant current source connected between the emitters of said first and second transistors and said second voltage terminal; a second current-mode logic circuit section which includes a third, a fourth and a fifth transistor with their respective emitters commonly connected, a sixth transistor with its collector connected to the emitters of said third, fourth and fifth transistors, a first logic signal input terminal connected to the base of said third transistor, and a first reference potential application terminal connected to the base of said fifth transistor, the collector of said third transistor being connected to the collector of said second transistor, the collector of said fourth transistor being connected to said first voltage terminal and its base being connected to the collector of said second transistor via an emitter follower, and the collector of said fifth transistor being connected to the collector of said first transistor; a third current-mode logic circuit section which includes a seventh, an eighth and a ninth transistor with their respective emitters commonly connected, a tenth transistor with its collector connected to the emitters of said seventh, eighth and ninth transistors, a second logic signal input terminal connected to the base of said seventh transistor, and a second reference potential application terminal connected to the base of said tenth transistor, the collector of said seventh transistor being connected to the collector of said third transistor, the collector of said eighth transistor being connected to said first voltage terminal and its base being connected to the base of said fourth transistor, and the collector of said ninth transistor being connected to the collector of said fifth transistor and its base being connected to said first reference potential application terminal; a second constant current source connected between the emitters of said sixth and tenth transistors and said second voltage terminal which is shared by said second and third current-mode logic circuit parts; a selection circuit section which includes an eleventh transistor that has its collector connected to the first voltage terminal, its emitter being connected to the base of said transistor and also to said second voltage terminal via a resistor, and a selection terminal connected to the base of said eleventh transistor; and a logic output terminal connected via an emitter-follower to a junction of collectors of said first, fifth and ninth transistors.

Claim 10

In a collector-dotted current-mode logic circuit as claimed in claim 1, 2 or 3, the collector-dotted current-mode logic circuit, and an output transistor having its base connected to the collector of said second transistor, its collector connected to the first voltage terminal, and its emitter connected to said second voltage terminal via a resistor; and the logic output being taken out from the emitter of said output transistor.

Claim 11

A current-mode logic circuit comprising: a first, a second, a third, a fourth and a fifth transistor, each having a first and a second current terminal and a control terminal; a first constant current source with one terminal commonly connected to the second current terminal of said first and second transistors and another terminal of said first constant current source connected to a first terminal of a two terminal power supply; a second constant current source with one terminal commonly connected to the second current terminals of said third, fourth and fifth transistors and another terminal connected to the first terminal of said power supply; first means commonly connecting the first current terminals of said first and third transistors and also connecting these terminals to the other terminal of said power supply; a load means having one terminal commonly connected to said current terminals of said second and fourth transistors and another terminal connected to the other terminal of said power supply; a second means for transmitting a potential of said first current terminals of said and third transistors to the control terminal of said fifth transistor; a first logic signal terminal connected to the control terminal of said first transistor; a second logic signal input terminal connected to the control terminal of said third transistor; a reference potential input terminal connected to the control terminals of said second and fourth transistors; a logic signal output terminal; and third means for transmitting a signal at the first current terminal of said second and fourth transistors to said logic signal output terminal; whereby the first current terminal of said fifth transistor is connected to the other terminal of said power supply.

Claim 12

A current-mode logic circuit comprising: a first, a second, a third, a fourth and a fifth transistor, each having a first and a second current terminal and a control terminal; a first constant current source with one terminal commonly connected to the second current terminal of said first and second transistors and another terminal of said first constant current source connected to a first terminal of a two terminal power supply; a second constant current source with one terminal commonly connected to the second current terminals of said third, fourth and fifth transistors and another terminal connected to the first terminal of said power supply; first means commonly connecting the first current terminals of said first and third transistors and also connecting these terminals to the other terminal of said power supply; a load means having one terminal commonly connected to said current terminals of said second and fourth transistors and another terminal connected to the other terminal of said power supply; a second means for transmitting a potential of said first current terminals of said and third transistors to the control terminal of said fifth transistor; a first logic signal terminal connected to the control terminal of said first transistor; a second logic signal input terminal connected to the control terminal of said third transistor; a reference potential input terminal connected to the control terminals of said second and fourth transistors; a logic signal output terminal; and third means for transmitting a signal at the first current terminal of said second and fourth transistors to said logic signal output terminal; whereby the first current terminal of said fifth transistor is connected to the other terminal of said power supply.

Claim 13

A current-mode logic circuit as claimed in claim 7, wherein said first means includes load means and clamping means that are connected in parallel.

Claim 14

A current-mode logic circuit as claimed in claim 7, wherein said second means includes a sixth transistor the control terminal of said sixth transistor is connected to the first current terminal of said first and third transistor, the first current terminal of said sixth transistor is connected to the other terminal of said power supply, and the second current terminal of said sixth transistor is connected to the control terminal of said fifth transistor as well as to the one terminal of said power supply via a resistor.

Claim 15

A collector-dotted current-mode circuit comprising: a first current-mode logic circuit section which includes a first and a second transistor with their respective emitters commonly connected, a first load resistor connected between the collector of said first transistor and a first voltage terminal, a second load resistor and a clamping diode connected in parallel between the collector of said second transistor and said first voltage terminal, and a first constant current source connected between the emitters of said first and second transistors and a second voltage terminal; a second current-mode logic circuit section which includes a plurality of current-mode logic circuits, each of these circuit having a third, a fourth and a fifth transistor with their respective emitters commonly connected, a logic signal input terminal connected to the base of said third transistor, a reference potential application terminal connected to the base of said fifth transistor, with the collector of said fourth transistor being connected to the first voltage terminal, a two terminal switching circuit having one of its terminals connected to said commonly connected emitters of said third, fourth and fifth transistors of each of the current-mode logic circuit and the other of its terminals commonly connected, and a second constant current source connected between said switching circuit and said second voltage terminal, the collectors of said third transistors of said plurality of current-mode logic circuits being connected to the collector of said second transistor, the bases of said fourth transistors being connected directly to the collector of said second transistor, and the collectors of said fifth transistors being connected to the collector of said first transistor; and means for selecting one of said plurality of current-mode logic circuits of said second current-mode logic circuit section by controlling said switching circuit and setting it at the on-state; whereby the low level at the collector of said second transistor is maintained constant regardless of the input level of the logic signals input to said first current-mode logic circuit part and said selected CML circuit.

Claim 16

A collector-dotted current-mode circuit comprising: a first current-mode logic circuit section which includes a first and a second transistor with their respective emitters commonly connected, a first load resistor connected between the collector of said first transistor and a first voltage terminal, a second load resistor and a clamping diode connected in parallel between the collector of said second transistor and said first voltage terminal, and a first constant current source connected between the emitters of said first and second transistors and a second voltage terminal; a second current-mode logic circuit section which includes a plurality of current-mode logic circuits, each of these circuit having a third, a fourth and a fifth transistor with their respective emitters commonly connected, a logic signal input terminal connected to the base of said third transistor, a reference potential application terminal connected to the base of said fifth transistor, with the collector of said fourth transistor being connected to the first voltage terminal, a two terminal switching circuit having one of its terminals connected to said commonly connected emitters of said third, fourth and fifth transistors of each of the current-mode logic circuit and the other of its terminals commonly connected, and a second constant current source connected between said switching circuit and said second voltage terminal, the collectors of said third transistors of said plurality of current-mode logic circuits being connected to the collector of said second transistor, the bases of said fourth transistors being connected directly to the collector of said second transistor, and the collectors of said fifth transistors being connected to the collector of said first transistor; and means for selecting one of said plurality of current-mode logic circuits of said second current-mode logic circuit section by controlling said switching circuit and setting it at the on-state; whereby the low level at the collector of said second transistor is maintained constant regardless of the input level of the logic signals input to said first current-mode logic circuit part and said selected CML circuit.

Claim 17

An AND gate circuit with an enable signal terminal comprising: a first current-mode logic circuit section which includes a first and a second transistor with their respective emitters commonly connected, a first load resistor connected between the collector of said first transistor and a first voltage terminal, a second load resistor and a clamping diode connected in parallel between the collector of said second transistor and said first voltage terminal, and a first constant current source connected between the emitters of said first and second transistor and said second voltage terminal; a second current-mode circuit section which includes a third, a fourth and a fifth transistor with their respective emitters commonly connected, a sixth transistor with its collector connected to the emitters of said third, fourth and fifth transistors, a first logic signal input terminal connected to the base of said third transistor, and a first reference potential application terminal connected to the base of said fifth transistor, the collector of said third transistor being connected to the collector of said second transistor, the collector of said fourth transistor being connected to said first voltage terminal and its base being connected directly to the collector of said second transistor, and the collector of said fifth transistor being connected to the collector of said first transistor; a third current-mode logic circuit section which includes a seventh, an eighth and a ninth transistor with their respective emitters commonly connected, a tenth transistor with its collector connected to the emitters of said seventh, eighth and ninth transistors, a second logic signal input terminal connected to the base of said seventh transistor, and a second reference potential application terminal connected to the base of said tenth transistor, the collector of said seventh transistor being connected to the collector of said third transistor, the collector of said eighth transistor being connected to said first voltage terminal and its base being connected to the base of said fourth transistor, and the collector of said ninth transistor being conneced to the collector of said fifth transistor and its base being connected to said first reference potential application terminal; a second constant current source connected between the emitters of said sixth and tenth transistors and said second voltage terminal which is shared by said second and third current-mode logic circuit parts; a selection circuit section which includes an eleventh transistor that has its collector connected to the first voltage terminal, its emitter being connected to the base of said sixth transistor and also to said second voltage terminal via a resistor, and a selection terminal connected to the base of said eleventh transistor; and a logic output terminal connected via an emitter-follower to a junction of collectors of said first, fifth and ninth transistors.

Claim 18

An AND gate circuit with an enable signal terminal comprising: a first current-mode logic circuit section which includes a first and a second transistor with their respective emitters commonly connected, a first load resistor connected between the collector of said first transistor and a first voltage terminal, a second load resistor and a clamping diode connected in parallel between the collector of said second transistor and said first voltage terminal, and a first constant current source connected between the emitters of said first and second transistor and said second voltage terminal; a second current-mode circuit section which includes a third, a fourth and a fifth transistor with their respective emitters commonly connected, a sixth transistor with its collector connected to the emitters of said third, fourth and fifth transistors, a first logic signal input terminal connected to the base of said third transistor, and a first reference potential application terminal connected to the base of said fifth transistor, the collector of said third transistor being connected to the collector of said second transistor, the collector of said fourth transistor being connected to said first voltage terminal and its base being connected directly to the collector of said second transistor, and the collector of said fifth transistor being connected to the collector of said first transistor; a third current-mode logic circuit section which includes a seventh, an eighth and a ninth transistor with their respective emitters commonly connected, a tenth transistor with its collector connected to the emitters of said seventh, eighth and ninth transistors, a second logic signal input terminal connected to the base of said seventh transistor, and a second reference potential application terminal connected to the base of said tenth transistor, the collector of said seventh transistor being connected to the collector of said third transistor, the collector of said eighth transistor being connected to said first voltage terminal and its base being connected to the base of said fourth transistor, and the collector of said ninth transistor being conneced to the collector of said fifth transistor and its base being connected to said first reference potential application terminal; a second constant current source connected between the emitters of said sixth and tenth transistors and said second voltage terminal which is shared by said second and third current-mode logic circuit parts; a selection circuit section which includes an eleventh transistor that has its collector connected to the first voltage terminal, its emitter being connected to the base of said sixth transistor and also to said second voltage terminal via a resistor, and a selection terminal connected to the base of said eleventh transistor; and a logic output terminal connected via an emitter-follower to a junction of collectors of said first, fifth and ninth transistors.