US6466504B1
Expired / Lapsed
US
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Compilable block clear mechanism on per I/O basis for high-speed memory
Assignee: Synopsys Inc
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Filing: 2000-06-08
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Granted: 2002-10-15
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Expires: 2020-06-08
Abstract
Abstract A circuit for selectively erasing a semiconductor memory instance on a per I/O basis. The circuit is provided as a tilable architectural element in a memory compiler for the semiconductor memory instance. A plurality of pass gates are disposed between global wordlines provided by the row decoder of the memory array and local wordlines that select memory bit cells in a particular I/O. One or more memory clear signals are used to decouple the local wordlines from the global wordlines and to connect them to a high voltage node, V DD . The I/O is cleared by placing a predetermined logic state (typically 0 ) on the bitline nodes of the I/O and selectively coupling the local wordlines to the V DD node.
Inventors
- 👤 Richard S. Roy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:54
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419; G11C7/00; G11C7/20; G11C2207/00; G11C2207/002
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
119 words
A circuit for selectively erasing a portion of a memory array, comprising: a plurality of pass gates, each of which is disposed between a global wordline emanating from a row decoder provided for said memory array and a local wordline coupled to a memory array portion; and a logic portion for alternatively coupling said local wordline to one of said global wordline and a high voltage node, said logic portion operating at least in part by actuating one of said plurality of pass gates corresponding to said global wordline, wherein said memory array portion is cleared by placing a predetermined logic on bitline nodes of said memory array portion and connecting said local wordline to said high voltage node.
Claim 2
Dependent Claim
119 words
A circuit for selectively erasing a portion of a memory array, comprising: a plurality of pass gates, each of which is disposed between a global wordline emanating from a row decoder provided for said memory array and a local wordline coupled to a memory array portion; and a logic portion for alternatively coupling said local wordline to one of said global wordline and a high voltage node, said logic portion operating at least in part by actuating one of said plurality of pass gates corresponding to said global wordline, wherein said memory array portion is cleared by placing a predetermined logic on bitline nodes of said memory array portion and connecting said local wordline to said high voltage node.
Claim 3
Dependent Claim
51 words
The circuit for selectively erasing a portion of a memory array as set forth in claim 1 , wherein said logic portion is operable in association with a memory clear signal and its complement, said complement signal activating a pull-up transistor coupled between said high voltage node and said local wordline.
Claim 4
Dependent Claim
56 words
The circuit for selectively erasing a portion of a memory array as set forth in claim 1 , wherein said logic portion is operable in association with a plurality of memory clear signals and their complements, each of said complement signals activating a pull-up transistor coupled between said high voltage node and a corresponding local wordline.
Claim 5
Dependent Claim
33 words
The circuit for selectively erasing a portion of a memory array as set forth in claim 1 , wherein said memory array portion comprises a plurality of static random access memory (SRAM) cells.
Claim 6
Dependent Claim
25 words
The circuit for selectively erasing a portion of a memory array as set forth in claim 4 , wherein each SRAM cell comprises six transistors.
Claim 7
Dependent Claim
28 words
The circuit for selectively erasing a portion of a memory array as set forth in claim 4 , wherein each SRAM cell comprises a predetermined number of transistors.
Claim 8
Dependent Claim
33 words
The circuit for selectively erasing a portion of a memory array as set forth in claim 1 , wherein said memory array portion comprises a plurality of dynamic random access memory (DRAM) cells.
Claim 9
Dependent Claim
34 words
The circuit for selectively erasing a portion of a memory array as set forth in claim 1 , further including a switch for disabling a V DD node associated with said memory array portion.
Claim 10
Dependent Claim
108 words
A memory compiler for use in designing an integrated semiconductor device having an embedded memory instance, comprising: a memory macro cell associated with said embedded memory instance, said memory macro cell including an array core with a row decoder for generating global wordlines; and at least one memory array input/output (I/O) block having a tilable circuit associated therewith to selectively erase memory bit cells therein, said tilable circuit operating to alternatively couple said memory cells in said at least one memory array I/O block to corresponding global wordlines generated by said row decoder during a normal memory operation and to a high voltage node in an erase operation.
Claim 11
Dependent Claim
108 words
A memory compiler for use in designing an integrated semiconductor device having an embedded memory instance, comprising: a memory macro cell associated with said embedded memory instance, said memory macro cell including an array core with a row decoder for generating global wordlines; and at least one memory array input/output (I/O) block having a tilable circuit associated therewith to selectively erase memory bit cells therein, said tilable circuit operating to alternatively couple said memory cells in said at least one memory array I/O block to corresponding global wordlines generated by said row decoder during a normal memory operation and to a high voltage node in an erase operation.
Claim 12
Dependent Claim
48 words
The memory compiler as set forth in claim 9 , wherein said tilable circuit includes a plurality of pass gates, each of which is disposed between one of said global wordlines generated from said row decoder and a corresponding local wordline disposed in said memory array I/O block.
Claim 13
Dependent Claim
25 words
The memory compiler as set forth in claim 10 , wherein said pass gates are actuated by at least one erase signal and its complement.
Claim 14
Dependent Claim
18 words
The memory compiler as set forth in claim 9 , wherein said array core comprises a SRAM core.
Claim 15
Dependent Claim
18 words
The memory compiler as set forth in claim 9 , wherein said array core comprises a DRAM core.
Claim 16
Dependent Claim
33 words
The memory compiler as set forth in claim 9 , wherein said tilable circuit comprises a switch to disable a V DD node associated with said memory bit cells in said I/O block.
Claim 17
Dependent Claim
102 words
A circuit for selectively clearing an I/O block in a memory array, comprising: a plurality of pass gates disposed between global wordlines generated by a row decoder associated with said memory array and local wordlines provided in said I/O block in said memory array; and means for alternatively coupling said local wordlines to said global wordlines in a normal memory operation and to a high voltage node in an erase operation, whereby said I/O block is erased when a predetermined logic state is applied at bitline nodes of said I/O block and said local wordlines are coupled to said high voltage node.
Claim 18
Dependent Claim
102 words
A circuit for selectively clearing an I/O block in a memory array, comprising: a plurality of pass gates disposed between global wordlines generated by a row decoder associated with said memory array and local wordlines provided in said I/O block in said memory array; and means for alternatively coupling said local wordlines to said global wordlines in a normal memory operation and to a high voltage node in an erase operation, whereby said I/O block is erased when a predetermined logic state is applied at bitline nodes of said I/O block and said local wordlines are coupled to said high voltage node.
Claim 19
Dependent Claim
23 words
The circuit as set forth in claim 15 , further comprising means to disable a V DD node associated with said I/O block.
Claim 20
Dependent Claim
33 words
The circuit as set forth in claim 15 , wherein said means for alternatively coupling is activated by a plurality of clear signals, each for erasing said I/O block in a staggered proportion.
Claim 21
Dependent Claim
35 words
The circuit as set forth in claim 15 , wherein said means for alternatively coupling is activated by a plurality of clear signals, each for erasing a portion of said I/O block in nonlinear increments.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-10-14 | 2006-04-15 | 2006-10-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-10-14 | 2010-04-15 | 2010-10-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-10-14 | 2014-04-15 | 2014-10-15 | $7700.00 | Window Closed / Lapsed |