Zero voltage drop negative switch for dual well processes

Claim 2

A negative switch circuit, comprising: a first voltage path coupled to an output of said negative switch circuit; a second voltage path coupled to said output of said negative switch circuit, said second voltage path includes at least one zero voltage drop switch, at least one of said zero voltage drop switches having a first switch device coupled to a bootstrapping circuit, said bootstrapping circuit including a first capacitive device and a second capacitive device wherein said bootstrapping device provides said second voltage path with a deselection current having a substantially zero current.

Claim 3

The negative switch circuit of claim 1, wherein said first switch device includes a first terminal coupled to said second capacitive device, a second terminal coupled to an input of said zero voltage drop switch circuit, and a third terminal coupled to an output of said zero voltage drop switch circuit, and wherein said bootstrapping circuit includes a second switch device having a first terminal coupled to said first capacitive device, a second terminal coupled to said input of said zero voltage drop switch circuit, and a third terminal coupled to said second capacitive device, and a third switch device having a first terminal coupled to said second capacitive device, a second terminal coupled to said input of said zero voltage drop switch circuit, and a third terminal coupled to said first capacitive device.

Claim 4

The negative switch circuit of claim 2, wherein said first switch device, said second switch device, and said third switch device are p-channel MOS transistors.

Claim 5

The negative switch circuit of claim 2, wherein said zero voltage drop switch circuit further includes a clock driver circuit coupled to said first capacitive device and said second capacitive device, said clock driver circuit provides a first non-overlapping clock signal to said first capacitive device and a second non-overlapping clock signal to said second capacitive device.

Claim 6

The negative switch circuit of claim 4, wherein said first non-overlapping clock signal and said second non-overlapping clock signal do not have overlapping logic low voltage levels.

Claim 7

A memory device, comprising: a memory array including at least one memory cell; and a decoding circuit coupled to said memory array, said decoding circuit including at least one negative switch circuit, at least one of said negative switch circuits includes at least one zero voltage drop switch circuit having a first switch device coupled to a bootstrapping circuit, said bootstrapping circuit including a first capacitive device and a second capacitive device wherein said bootstrapping device provides a deselection current having a substantially zero current.

Claim 8

A memory device, comprising: a memory array including at least one memory cell; and a decoding circuit coupled to said memory array, said decoding circuit including at least one negative switch circuit, at least one of said negative switch circuits includes at least one zero voltage drop switch circuit having a first switch device coupled to a bootstrapping circuit, said bootstrapping circuit including a first capacitive device and a second capacitive device wherein said bootstrapping device provides a deselection current having a substantially zero current.

Claim 9

The memory device of claim 6, wherein at least one of said memory cells is a flash EEPROM memory cell.

Claim 10

The memory device of claim 6, wherein said decoding circuit includes a row decoding circuit, a block decoding circuit, or a plane decoding circuit.

Claim 11

The memory device of claim 6, wherein said first switch is fabricated with a dual well process.

Claim 12

The memory device of claim 6, wherein at least one of said negative switch circuits includes a negative voltage path and a positive voltage path, said negative voltage path includes at least one of said zero voltage drop switch circuits, said negative voltage path provides a deselection current having substantially zero current.

Claim 13

The memory device of claim 6, wherein said first switch device includes a first terminal coupled to said second capacitive device, a second terminal coupled to an input of said zero voltage drop switch circuit, and a third terminal coupled to an output of said zero voltage drop switch circuit, and wherein said bootstrapping circuit includes a second switch device having a first terminal coupled to said first capacitive device, a second terminal coupled to said input of said zero voltage drop switch circuit, and a third terminal coupled to said second capacitive device, and a third switch device having a first terminal coupled to said second capacitive device, a second terminal coupled to said input of said zero voltage drop switch circuit, and a third terminal coupled to said first capacitive device.

Claim 14

The memory device of claim 11, wherein said first switch device, said second switch device, and said third switch device are p-channel MOS transistors.

Claim 15

The memory device of claim 11, wherein said zero voltage drop switch circuit further includes a clock driver circuit coupled to said first capacitive device and said second capacitive device, said clock driver circuit provides a first non-overlapping clock signal to said first capacitive device and a second non-overlapping clock signal to said second capacitive device.

Claim 16

The memory device of claim 13, wherein said first non-overlapping clock signal and said second non-overlapping clock signal do not have overlapping logic low voltage levels.

Claim 17

The memory device of claim 6, wherein at least one of said negative switch circuits includes a row negative switch, a block negative switch, or a plane negative switch.

Claim 18

The memory device of claim 6, wherein at least one of said zero voltage drop switch circuits includes a first zero voltage drop switch circuit and a second zero voltage drop switch circuit, said first zero voltage drop switch circuit has an input that receives a negative voltage signal from a negative charge pump, said first zero voltage drop switch circuit has an output coupled to an input of said second zero voltage drop switch circuit, said second zero voltage drop switch circuit has an output coupled to an output of said negative switch circuit.

Claim 19

A zero voltage drop switch circuit, comprising: a first capacitive device configured to receive a first non-overlapping clock signal; a second capacitive device configured to receive a second non-overlapping clock signal; a first switch device having a first terminal coupled to said second capacitive device, a second terminal coupled to an input of said zero voltage drop switch circuit, and a third terminal coupled to an output of said zero voltage drop switch circuit; a second switch device having a first terminal coupled to said first capacitive device, a second terminal coupled to said input of said zero voltage drop switch circuit, and a third terminal coupled to said second capacitive device; and a third switch device having a first terminal coupled to said second capacitive device, a second terminal coupled to said input of said zero voltage drop switch circuit, and a third terminal coupled to said first capacitive device.

Claim 20

A zero voltage drop switch circuit, comprising: a first capacitive device configured to receive a first non-overlapping clock signal; a second capacitive device configured to receive a second non-overlapping clock signal; a first switch device having a first terminal coupled to said second capacitive device, a second terminal coupled to an input of said zero voltage drop switch circuit, and a third terminal coupled to an output of said zero voltage drop switch circuit; a second switch device having a first terminal coupled to said first capacitive device, a second terminal coupled to said input of said zero voltage drop switch circuit, and a third terminal coupled to said second capacitive device; and a third switch device having a first terminal coupled to said second capacitive device, a second terminal coupled to said input of said zero voltage drop switch circuit, and a third terminal coupled to said first capacitive device.

Claim 21

The zero voltage drop switch circuit of claim 17 wherein said first switch device, said second switch device, and said third switch device are p-channel MOS transistors.

Claim 22

The zero voltage drop switch circuit of claim 17 further comprising a clock driver circuit coupled to said first capacitive device and said second capacitive device, said clock driver circuit provides a first non-overlapping clock signal to said first capacitive device and a second non-overlapping clock signal to said second capacitive device.

Claim 23

The zero voltage drop switch circuit of claim 17, wherein said first switch device is larger in size than said second switch device and said third switch device.

Claim 24

The zero voltage drop switch circuit of claim 17, wherein said first switch device, said second switch device, and said third switch device have substantially the same threshold voltages.

Claim 25

The zero voltage drop switch circuit of claim 18, wherein said first non-overlapping clock signal and said second non-overlapping clock signal do not have overlapping low logic levels.

Claim 28

The method of claim 23 further comprising the steps of: (f) providing said second voltage level to said first node during a second phase of said first and said second non-overlapping low clock input signals; (g) providing said first voltage level to said second node during said second phase; and (h) maintaining said first voltage level at said output of said switch circuit during said second phase.

Claim 29

The method of claim 23, wherein said first voltage level represents V in , said logic high voltage level represents V reg , and said logic low voltage level represents 0 volts.

Claim 30

The method of claim 23, further comprising prior to step (a), the step of: (i) powering up said switch circuit into its steady state.