Patent US6465306B1 successfully refreshed from Google Patents.
US6465306B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Simultaneous formation of charge storage and bitline to wordline isolation
Assignee: Longitude Flash Memory Solutions Ltd
•
Filing: 2000-11-28
•
Granted: 2002-10-15
•
Expires: 2020-11-28
Abstract
Abstract One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region.
Inventors
- 👤 Mark T. Ramsbey
- 👤 Jean Y. Yang
- 👤 Hidehiko Shiraiwa
- 👤 Michael A. Van Buskirk
- 👤 David M. Rogers
- 👤 Ravi Sunkavalli
- 👤 Janet Wang
- 👤 Narbeh Derhacobian
- 👤 Yider Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:34
CPC Classifications
H; H10; H10B; H10B43/00; H10B43/30; H10B43/40; H10B69/00; Y; Y10; Y10S; Y10S438/00; Y10S438/954; Y10S438/981
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
95 words
A method of forming a non-volatile semiconductor memory device, comprising: forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region with a proviso that the charge trapping dielectric is not etched in the core region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region, with a proviso that LOCOS is not formed in the core region.
Claim 2
Independent Claim
95 words
A method of forming a non-volatile semiconductor memory device, comprising: forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region with a proviso that the charge trapping dielectric is not etched in the core region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region, with a proviso that LOCOS is not formed in the core region.
Claim 3
Dependent Claim
29 words
The method according to claim 1 , wherein a portion of the charge trapping dielectric in the periphery region is removed before forming buried bitlines in the core region.
Claim 4
Dependent Claim
29 words
The method according to claim 1 , wherein buried bitlines are formed in the core region before removing the portion of the charge trapping dielectric in the periphery region.
Claim 5
Dependent Claim
25 words
The method according to claim 1 , wherein the gate dielectric is formed in the periphery region before forming buried bitlines in the core region.
Claim 6
Dependent Claim
25 words
The method according to claim 1 , wherein buried bitlines are formed in the core region before forming the gate dielectric in the periphery region.
Claim 7
Independent Claim
81 words
A method of forming a non-volatile semiconductor memory device, comprising sequentially: forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region, with a proviso that LOCOS is not formed in the core region.
Claim 8
Independent Claim
81 words
A method of forming a non-volatile semiconductor memory device, comprising sequentially: forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region, with a proviso that LOCOS is not formed in the core region.
Claim 9
Dependent Claim
23 words
The method according to claim 6 , wherein the charge trapping dielectric has a thickness from about 75 Å to about 300 Å.
Claim 10
Dependent Claim
23 words
The method according to claim 6 , wherein the buried bitlines are formed by implanting at least one of arsenic, boron, and phosphorus.
Claim 11
Dependent Claim
26 words
The method according to claim 6 , wherein the gate dielectric in the periphery region has a thickness from about 30 Å to about 300 Å.
Claim 12
Dependent Claim
32 words
The method according to claim 8 , wherein at least one of arsenic, boron, and phosphorus are implanted at a dosage from about 1×10 14 to about 1×10 16 atoms/cm 2 .
Claim 13
Dependent Claim
66 words
The method according to claim 6 , wherein the charge trapping dielectric comprises one of an ONO trilayer dielectric, an oxide/nitride bilayer dielectric, a nitride/oxide bilayer dielectric, an oxide/tantalum oxide bilayer dielectric, an oxide/tantalum oxide/oxide trilayer dielectric, an oxide/strontium titanate bilayer dielectric, an oxide/barium strontium titanate bilayer dielectric, an oxide/strontium titanate/oxide trilayer dielectric, an oxide/strontium titanate/barium strontium titanate trilayer dielectric, and an oxide/hafnium oxide/oxide trilayer dielectric.
Claim 14
Dependent Claim
30 words
The method according to claim 6 , wherein the charge trapping dielectric comprises an ONO dielectric comprising at least one of a nitrided oxide layer, a silicon-rich silicon nitride layer.
Claim 15
Dependent Claim
22 words
The method according to claim 6 , with a proviso that the charge trapping dielectric is not etched in the core region.
Claim 16
Independent Claim
81 words
A method of forming a non-volatile semiconductor memory device, comprising sequentially: forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; forming buried bitlines in the core region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; and forming gates in the core region and the periphery region, with a proviso that LOCOS is not formed in the core region.
Claim 17
Independent Claim
81 words
A method of forming a non-volatile semiconductor memory device, comprising sequentially: forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; forming buried bitlines in the core region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; and forming gates in the core region and the periphery region, with a proviso that LOCOS is not formed in the core region.
Claim 18
Dependent Claim
23 words
The method according to claim 14 , wherein the buried bitlines are formed by implanting at least one of arsenic, boron, and phosphorus.
Claim 19
Dependent Claim
26 words
The method according to claim 14 , wherein the gate dielectric in the periphery region has a thickness from about 30 Å to about 300 Å.
Claim 20
Dependent Claim
66 words
The method according to claim 14 , wherein the charge trapping dielectric comprises one of an ONO trilayer dielectric, an oxide/nitride bilayer dielectric, a nitride/oxide bilayer dielectric, an oxide/tantalum oxide bilayer dielectric, an oxide/tantalum oxide/oxide trilayer dielectric, an oxide/strontium titanate bilayer dielectric, an oxide/barium strontium titanate bilayer dielectric, an oxide/strontium titanate/oxide trilayer dielectric, an oxide/strontium titanate/barium strontium titanate trilayer dielectric, and an oxide/hafnium oxide/oxide trilayer dielectric.
Claim 21
Dependent Claim
22 words
The method according to claim 14 , wherein the buried bitlines have a width from about 0.18 μm to about 1 μm.
Claim 22
Dependent Claim
23 words
The method according to claim 14 further comprising performing a blanket threshold implant prior to forming the charge trapping dielectric over the substrate.
Claim 23
Dependent Claim
31 words
The method according to claim 14 further comprising performing a threshold implant after forming the charge trapping dielectric over the substrate and prior to forming buried bitlines in the core region.
Claim 24
Dependent Claim
22 words
The method according to claim 14 , with a proviso that the charge trapping dielectric is not etched in the core region.
References Cited (Backward Citations)
US4173766A
Cited
US5168334A
Cited
JPH03227069A
Cited
US5349221A
Cited
US5644533A
Cited
JPH06291330A
Cited
JP3227069B2
Cited
US5825686A
Cited
US5751037A
Cited
US5768192A
Cited
US5966603A
Cited
US6011725A
Cited
US5963465A
Cited
US6001709A
Cited
US6030871A
Cited
WO1999060631A1
Cited
US6287917B1
Cited
US6117730A
Cited
US6326268B1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-10-14 | 2006-04-15 | 2006-10-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-10-14 | 2010-04-15 | 2010-10-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-10-14 | 2014-04-15 | 2014-10-15 | $7700.00 | Window Closed / Lapsed |