US6463008B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit device
Assignee: NEC Electronics Corp
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Filing: 2002-01-07
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Granted: 2002-10-08
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Expires: 2022-01-07
Abstract
Abstract A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.
Inventors
- 👤 Yuichi Okuda
- 👤 Masaru Kokubo
- 👤 Yoshinobu Nakagome
- 👤 Hideharu Yahata
- 👤 Hiroki Miyashita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:17
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C29/00; G11C29/02; G11C29/023; G11C29/028; G11C29/04; G11C29/08; G11C29/12; G11C29/12005; G11C5/00; G11C5/02; G11C5/025; G11C7/00; G11C7/10; G11C7/1072; G11C7/22; G11C7/222; G11C8/00; G11C8/12; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03L7/085; H03L7/089; H03L7/0891; H03L7/0895; H03L7/0898; H03L7/10; H03L7/107; H03L7/1072; H03L2207/00; H03L2207/14
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
196 words
A semiconductor integrated circuit device comprising: a clock-generating circuit that includes a variable delay circuit for producing second clock signals by delaying, by a predetermined delay time, first clock signals that are formed based upon clock signals input through an external terminal, and a control circuit for comparing the phase of third clock signals formed based on the second clock signals with the phase of the first clock signals and for so controlling the delay time that the difference between the phases is decreased; and an internal circuit that operates in response to the second clock signals; which are formed on a common semiconductor substrate; wherein an element-forming region constituting the variable delay circuit is isolated from an element-forming region constituting the internal circuit; and wherein: the delay time is controlled by an analog voltage; the control circuit includes a phase comparator circuit which compares the phase of the first clock signals with the phase of the third clock signals and produces control signals, and a charge pump circuit that generates the analog voltage based on the control signals; and the charge pump circuit is electrically isolated from the element-forming region that constitutes the internal circuit.
Claim 2
Dependent Claim
196 words
A semiconductor integrated circuit device comprising: a clock-generating circuit that includes a variable delay circuit for producing second clock signals by delaying, by a predetermined delay time, first clock signals that are formed based upon clock signals input through an external terminal, and a control circuit for comparing the phase of third clock signals formed based on the second clock signals with the phase of the first clock signals and for so controlling the delay time that the difference between the phases is decreased; and an internal circuit that operates in response to the second clock signals; which are formed on a common semiconductor substrate; wherein an element-forming region constituting the variable delay circuit is isolated from an element-forming region constituting the internal circuit; and wherein: the delay time is controlled by an analog voltage; the control circuit includes a phase comparator circuit which compares the phase of the first clock signals with the phase of the third clock signals and produces control signals, and a charge pump circuit that generates the analog voltage based on the control signals; and the charge pump circuit is electrically isolated from the element-forming region that constitutes the internal circuit.
Claim 3
Dependent Claim
71 words
A semiconductor integrated circuit device according to claim 1 , wherein the circuits such as variable delay circuit and charge pump circuit are formed on a well region of a second type of electric conduction that is deeply formed, and on a well region of a first type of electric conduction or of the second electric conduction shallowly formed on a common semiconductor substrate of the first type of electric conduction.
Claim 4
Dependent Claim
64 words
A semiconductor integrated circuit device according to claim 1 , wherein: the semiconductor integrated circuit device has a first supply unit for supplying a first voltage and a second supply unit for supplying the first voltage; the internal circuit receives the first voltage supplied from the first supply unit; and the variable delay circuit receives the first voltage supplied from the second supply unit.
Claim 5
Dependent Claim
179 words
A semiconductor integrated circuit device comprising: a clock-generating circuit that includes a variable delay circuit for producing second clock signals by delaying, by a predetermined delay time, first clock signals that are formed based upon clock signals input through an external terminal, and a control circuit for comparing the phase of third clock signals formed based on the second clock signals with the phase of the first clock signals and for so controlling the delay time that the difference between the phases is decreased; and an internal circuit that operates in response to the second clock signals; which are formed on a common semiconductor substrate; wherein an element-forming region constituting the variable delay circuit is isolated from an element-forming region constituting the internal circuit; and wherein: the semiconductor integrated circuit device has a first supply unit for supplying a first voltage and a second supply unit for supplying the first voltage; the internal circuit receives the first voltage supplied from the first supply unit; and the variable delay circuit receives the first voltage supplied from the second supply unit.
Claim 6
Dependent Claim
179 words
A semiconductor integrated circuit device comprising: a clock-generating circuit that includes a variable delay circuit for producing second clock signals by delaying, by a predetermined delay time, first clock signals that are formed based upon clock signals input through an external terminal, and a control circuit for comparing the phase of third clock signals formed based on the second clock signals with the phase of the first clock signals and for so controlling the delay time that the difference between the phases is decreased; and an internal circuit that operates in response to the second clock signals; which are formed on a common semiconductor substrate; wherein an element-forming region constituting the variable delay circuit is isolated from an element-forming region constituting the internal circuit; and wherein: the semiconductor integrated circuit device has a first supply unit for supplying a first voltage and a second supply unit for supplying the first voltage; the internal circuit receives the first voltage supplied from the first supply unit; and the variable delay circuit receives the first voltage supplied from the second supply unit.
Claim 7
Dependent Claim
51 words
A semiconductor integrated circuit device according to claim 1 or 4 , wherein a MOS capacitor element is formed in the periphery of a well region of the second type of electric conduction that is deeply formed, and is used for stabilizing the first voltage supplied to the variable delay circuit.
Claim 8
Dependent Claim
87 words
A semiconductor integrated circuit device according to claim 1 or 4 , wherein the clock-generating circuit further has a clock input buffer that produces the first clock signals upon receiving the input clock signals, and a clock output buffer that produces fourth clock signals upon receiving the second clock signals; the internal circuit operates upon receiving the fourth clock signals; and the clock input buffer and the clock output buffer are formed on a well region of the second type of electric conduction that is deeply formed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-10-07 | 2006-04-08 | 2006-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-10-07 | 2010-04-08 | 2010-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-10-07 | 2014-04-08 | 2014-10-08 | $7700.00 | Window Closed / Lapsed |