US6462596B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Reduced-transistor, double-edged-triggered, static flip flop
Assignee: International Business Machines Corp
•
Filing: 2000-06-23
•
Granted: 2002-10-08
•
Expires: 2020-06-23
Abstract
Abstract A static, double-edge-triggered flip-flop has an upper data path and a lower data path connected between a data input node and an output terminal. The upper path includes a switch connected to a first data loop, and the lower path includes a switch connected to a second data loop. The first and second data loops share a forward path having a data-inverting circuit. In addition, each loop has a feedback path which contains only one element in the form of a switch. However, no data-inverting circuit is included in either of the feedback paths. Advantageously, all the elements of the flip-flop may be constructed using MOSFET transistors implemented according to any one of a variety of semiconductor technologies. In more than one particularly advantageous embodiments, the flip-flop is constructed using a total of twelve transistors. Through this simplified two-loop design, operational efficiency is improved, low metastability is achieved and costs of manufacture are lowered, all while maintaining low power requirements.
Inventors
- 👤 Pradeep Varma
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 00:32
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104; H03K3/356165; H03K3/356173; H03K3/356113; H03K3/356147; H03K3/356156; H03K3/01; H03K3/012
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
221 words
A static, double-edge triggered flip-flop comprising: an input terminal; an output terminal; a first switch passing data from the input terminal to a first intermediate node on a clock signal; a first data loop connected between said first intermediate node and said output terminal, wherein said fist data loop includes: (a) a first forward path having a clocked inverter which operates based on a complementary clock signal; (b) a shared path connected to an output of said first forward pat; and (c) a first feedback path connected from an output of said shared path to an input of said first forward path; and a second switch passing data from the input terminal to a second intermediate node on said complementary clock signal second data loop connected between said second intermediate node and said output terminal, wherein said second data loop includes: (a) a second forward pat having a clocked inverter which operates based on said clock signal; (b) said shared path connected to an output of said second forward pat; and (c) a second feedback path connected from an output of said shared path to an input of said second forward path, wherein said shared path of said first and second data loops includes an inverter for inverting data output from the clocked inverters in said first and second for paths.
Claim 2
Dependent Claim
221 words
A static, double-edge triggered flip-flop comprising: an input terminal; an output terminal; a first switch passing data from the input terminal to a first intermediate node on a clock signal; a first data loop connected between said first intermediate node and said output terminal, wherein said fist data loop includes: (a) a first forward path having a clocked inverter which operates based on a complementary clock signal; (b) a shared path connected to an output of said first forward pat; and (c) a first feedback path connected from an output of said shared path to an input of said first forward path; and a second switch passing data from the input terminal to a second intermediate node on said complementary clock signal second data loop connected between said second intermediate node and said output terminal, wherein said second data loop includes: (a) a second forward pat having a clocked inverter which operates based on said clock signal; (b) said shared path connected to an output of said second forward pat; and (c) a second feedback path connected from an output of said shared path to an input of said second forward path, wherein said shared path of said first and second data loops includes an inverter for inverting data output from the clocked inverters in said first and second for paths.
Claim 3
Dependent Claim
29 words
The flip-flop of claim 1 , wherein said clock signal and said complementary clock signal are different phases of a same clock signal output from a single clock circuit.
Claim 4
Dependent Claim
65 words
The flip-flop of claim 1 , wherein said first switch operates on said clock signal and the clocked inverter in said first forward path of said first data loop operates on said complementary clock signal, and wherein said second switch operates on said complementary clock signal and the clocked inverter in said second forward path of said second data loop operates on said clock signal.
Claim 5
Dependent Claim
53 words
The flip-flop of claim 1 , wherein said first feedback path includes a first feedback switch for controlling data flow from the output terminal to said first forward path, and wherein said second feedback path includes a second feedback switch for controlling data flow from the output terminal to said second forward path.
Claim 6
Dependent Claim
43 words
The flip-flop of claim 1 , wherein said first switch, said second switch, the clocked inverters in said first and second forward paths, said first feedback switch, said second feedback switch, and the inverter in said shared path are implemented using only MOSFETs.
Claim 7
Dependent Claim
54 words
The flip-flop of claim 1 , wherein said first switch, said second switch, the clocked inverters in said first and second forward paths, said first feedback switch, said second feedback switch, and the inverter in said shared path are implemented using CMOS technology so that one of twelve or fourteen total MOSFETs are used.
Claim 8
Dependent Claim
46 words
The flip-flop of claim 1 , wherein said first switch, said second switch, the clocked inverters in said first and second forward paths, said first feedback switch, said second feedback switch, and the inverter in said shared path are implemented using MOS style in CMOS technology.
Claim 9
Dependent Claim
55 words
The flip-flop of claim 1 , wherein said first switch, said second switch, the clocked inverters in said first and second forward paths, said first feedback switch, said second feedback switch, and the inverter in said shared path are implemented using only NMOS transistors so that one of twelve or fourteen total MOSFETs are used.
Claim 10
Dependent Claim
55 words
The flop-flop of claim 1 , wherein said first switch, said second switch, the clocked inverters in said first and second forward paths, said first feedback switch, said second feedback switch, and the inverter in said shared path are implemented using only PMOS transistors so that one of twelve or fourteen total MOSFETs are used.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-10-07 | 2006-04-08 | 2006-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-10-07 | 2010-04-08 | 2010-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-10-07 | 2014-04-08 | 2014-10-08 | $7700.00 | Window Closed / Lapsed |