US6188636B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit configuration for data storage
Assignee: Infineon Technologies AG
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Filing: 1998-09-21
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Granted: 2001-02-13
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Expires: 2018-09-21
Abstract
Abstract A circuit configuration for storing data has a first clocked register structure connected in parallel with a second register structure. The second register structure is operated in a push-pull mode relative to the first register structure. As a result, changes in the state of an input signal at the input are stored for each clock phase of a clock signal. Therefore, the clocking of the input signal of the circuit configuration can be done at the clock rate of the clock signal.
Inventors
- 👤 Oliver Salomon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 01:50
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1078; G11C7/1093; G11C7/1051; G11C7/106; H; H03; H03K; H03K3/00; H03K3/01; H03K3/012; H03K3/02; H03K3/027; H03K3/037
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
266 words
A circuit configuration, comprising: an input terminal for receiving data; an output terminal for outputting data; a first memory device for storing data and having an output and an input; a second memory device for storing data and having an output and an input; a first input switch having one side connected to said input terminal and another side connected to said input of said first memory device, said first input switch responsive to an applied clock signal for connecting said input of said first memory device to said input terminal during a first logic state of the clock signal; a second input switch having one side connected to said input terminal and another side connected to said input of said second memory device, said second input switch responsive to the clock signal for connecting said input of said second memory device to said input terminal during a second logic state of the clock signal; a first output transistor including a drain-source path with one side connected to said output of said first memory device and another side connected to said output terminal, said first output transistor configured to connect said output of said first memory device to said output terminal during the second logic state of the clock signal; and a second output transistor including a drain-source path with one side connected to said output of said second memory device and another side connected to said output terminal, said second output transistor configured to connect said output of said second memory device to said output terminal during the first logic state of the clock signal.
Claim 2
Dependent Claim
266 words
A circuit configuration, comprising: an input terminal for receiving data; an output terminal for outputting data; a first memory device for storing data and having an output and an input; a second memory device for storing data and having an output and an input; a first input switch having one side connected to said input terminal and another side connected to said input of said first memory device, said first input switch responsive to an applied clock signal for connecting said input of said first memory device to said input terminal during a first logic state of the clock signal; a second input switch having one side connected to said input terminal and another side connected to said input of said second memory device, said second input switch responsive to the clock signal for connecting said input of said second memory device to said input terminal during a second logic state of the clock signal; a first output transistor including a drain-source path with one side connected to said output of said first memory device and another side connected to said output terminal, said first output transistor configured to connect said output of said first memory device to said output terminal during the second logic state of the clock signal; and a second output transistor including a drain-source path with one side connected to said output of said second memory device and another side connected to said output terminal, said second output transistor configured to connect said output of said second memory device to said output terminal during the first logic state of the clock signal.
Claim 3
Dependent Claim
35 words
The circuit configuration according to claim 1 , wherein said first output transistor is of a first conduction type and said second output transistor is of a second conduction type opposite said first conduction type.
Claim 4
Dependent Claim
27 words
The circuit configuration of claim 1 , wherein at least one of said first memory device and said second memory device has a pair of anti-parallel-connected inverters.
Claim 5
Dependent Claim
39 words
The circuit configuration according to claim 1 , wherein at least one of said first memory device and said second memory device has an output terminal and a storage capacitor connected between said output terminal and a reference potential.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-02-13 | 2004-08-14 | 2005-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-02-13 | 2008-08-14 | 2009-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-02-13 | 2012-08-14 | 2013-02-13 | $7700.00 | Window Closed / Lapsed |