Circuit and method for sampling digital data

Claim 2

A sampling circuit comprising: first sampling means, responsive to a clock pulse, having a signal level, for receiving input data when the clock pulse signal level is in a first state, the first sampling means comprising a first input gate driven by the clock pulse; first holding means for holding the input data which is received via said first input gate; and a first output gate, driven by the clock pulse, for delivering hold data of said first holding means when the clock pulse signal level is in a second state; second sampling means, responsive to the clock pulse, for receiving the input data when the clock pulse signal level is in the second state, the second sampling means comprising a second input gate driven by the clock pulse; second holding means for holding the input data which is received via said second input gate; and a second output gate for delivering the hold data of said second holding means when the clock pulse signal level is in the first state; and data control means, operated by an external control signal, for delivering the data held in the first and second holding means to the first and second output gates when the external control signal is not present; for inhibiting delivery of the data held in the first and second holding means to the first and second output gates when the external control signal is present; and for delivering predetermined data to the first and second output gates when the external control signal is present.

Claim 3

The sampling circuit according to claim 1, wherein when the external control signal is a preset signal, said data control means delivers the predetermined data having a predetermined level.

Claim 4

The sampling circuit according to claim 1, wherein when the external control signal is a reset signal, said data control means generates the predetermined data having a predetermined level.

Claim 5

The sampling circuit according to claim 1, wherein the external control signal has a preset signal and a reset signal, and said data control means delivers the predetermined data having a first level in response to the preset signal and the predetermined data having a second level in response to the reset signal.

Claim 6

The sampling circuit according to claim 1, wherein said first and second input gates, said first and second holding means and said first and second output gates have respective control gates controlled by the clock pulse and constitute an inverter logic circuit; said data control means comprises first and second gate circuits having respective gates controlled by said control means; said first and second input gates have input terminals supplied with the input data; said first input gate has an output terminal connected via said first gate circuit in said data control means to input terminals of said first output gate and first holding means; said first holding means has an output terminal connected to output terminal of said first input gate; said second input gate has an output terminal connected via said gate circuit in said data control means to inputs of said second output gate and second holding means; said second holding means has an output terminal connected to said output terminal of said second input gate; said first input gate, second holding means and second output gate are operated when the clock pulse supplied to their control gates has a signal level of the first state; and said second input gate, first holding means and first output gate are operated when the clock pulse supplied to their control gates has a signal level of the second state.

Claim 7

A sampling circuit comprising: first sampling means, responsive to a clock pulse, for receiving input data when the clock pulse has a first level, the first sampling means comprising a first input gate driven by the clock pulse: first holding means for holding the input data which is received via said first input gate; and a first output gate driven by the clock pulse to output the hold data of said first holding means when the clock pulse has a second level; and second sampling means, responsive to the clock pulse, for receiving the input data when the clock pulse has the second level, the second sampling means comprising a second input gate driven by the clock pulse; second holding means for holding data which is received via said second input gate; and a second output gate driven by the clock pulse to output the hold data of said second holding means when the clock pulse has the first level; and wherein the first and second input gates, the first and second holding means, and the first and second output gates have respective gates controlled by the clock pulse and constitute an inverter logic circuit; the first and second input gates have input terminals supplied with the input data; the first input gate has an output terminal connected to inputs of said first output gate and the first holding means; the first holding means have an output terminal connected to the output terminal of the first input gate; the second input gate has an output terminal connected to inputs of the second output gate and the second holding means; the second holding means has an output terminal connected to the output terminal of the second input gate, the first input gate, and the second holding means; the second output gate is operated when the clock pulse, supplied to their control gates, is at the first level; and the second input gate, the first holding means, and the first output gate is operated when the clock pulse, supplied to their control gates, is at the second level.

Claim 8

A sampling circuit comprising: first sampling means, responsive to a clock pulse, for receiving input data when the clock pulse has a first level, the first sampling means comprising a first input gate driven by the clock pulse: first holding means for holding the input data which is received via said first input gate; and a first output gate driven by the clock pulse to output the hold data of said first holding means when the clock pulse has a second level; and second sampling means, responsive to the clock pulse, for receiving the input data when the clock pulse has the second level, the second sampling means comprising a second input gate driven by the clock pulse; second holding means for holding data which is received via said second input gate; and a second output gate driven by the clock pulse to output the hold data of said second holding means when the clock pulse has the first level; and wherein the first and second input gates, the first and second holding means, and the first and second output gates have respective gates controlled by the clock pulse and constitute an inverter logic circuit; the first and second input gates have input terminals supplied with the input data; the first input gate has an output terminal connected to inputs of said first output gate and the first holding means; the first holding means have an output terminal connected to the output terminal of the first input gate; the second input gate has an output terminal connected to inputs of the second output gate and the second holding means; the second holding means has an output terminal connected to the output terminal of the second input gate, the first input gate, and the second holding means; the second output gate is operated when the clock pulse, supplied to their control gates, is at the first level; and the second input gate, the first holding means, and the first output gate is operated when the clock pulse, supplied to their control gates, is at the second level.

Claim 9

An input data sampling method, for use in a data sampling apparatus having a single input terminal and a single output terminal, and for sampling data input from the single input terminal and outputting sampled data through the single output terminal, the sampling method comprising the steps of: receiving, upon receipt of a clock pulse signal level in a first state, data input from the single input terminal, in synchronism with a clock pulse, of a frequency, and holding it as first hold data; outputting the first hold data through the single output terminal when a signal level of the clock pulse signal is in a second state; receiving the data input from the single input terminal when the signal level of the clock pulse is in the second state and holding it as second hold data; outputting the second hold data through the single output terminal when the signal level of the clock pulse is in the first state; and outputting, in place of the first and second hold data, predetermined data in accordance with a control signal; wherein the first and second hold data and the predetermined data are outputted as output data to the single output terminal at a frequency of up to twice the frequency of the clock pulse.

Claim 10

An input data sampling method, for use in a data sampling apparatus having a single input terminal and a single output terminal, and for sampling data input from the single input terminal and outputting sampled data through the single output terminal, the sampling method comprising the steps of: receiving, upon receipt of a clock pulse signal level in a first state, data input from the single input terminal, in synchronism with a clock pulse, of a frequency, and holding it as first hold data; outputting the first hold data through the single output terminal when a signal level of the clock pulse signal is in a second state; receiving the data input from the single input terminal when the signal level of the clock pulse is in the second state and holding it as second hold data; outputting the second hold data through the single output terminal when the signal level of the clock pulse is in the first state; and outputting, in place of the first and second hold data, predetermined data in accordance with a control signal; wherein the first and second hold data and the predetermined data are outputted as output data to the single output terminal at a frequency of up to twice the frequency of the clock pulse.

Claim 11

The method according to claim 7, wherein the control signal is a preset signal.

Claim 12

The method according to claim 7, wherein the control signal is a reset signal.

Claim 13

The method according to claim 7, wherein the predetermined data has selectively first and second states, and the control signal comprises one of a preset signal and a reset signal, whereby the predetermined data has the first state when the control signal is the preset signal and the second state when the control signal is the reset signal.