Semiconductor memory device with latch-up suppression

Abstract

Abstract A semiconductor memory device has a semiconductor substrate, a peripheral circuit region and a memory cell region on the principal surface of the semiconductor substrate. The semiconductor memory device has a first well formed in the peripheral circuit region, a second well of first conductivity type and a third well of second conductivity type formed in the memory cell region having substantially the same depth, and a device element isolator formed in the memory cell region for isolating a device element formed in the second well from a device element formed in the third well. The second and third wells extend to an area under the device element isolator. The second and third wells extend to a level under the device element isolator. The second and third wells may include a first layer having a depth shallower than the first well, and a second layer having substantially the same depth as the first well. The first layer of the second well overlaps the first layer of the third well under the device element isolator. The second layer of the second well and the second layer of the third well are isolated from each other. The depth of the first layer in the second and third wells formed in the memory cell region may be shallower than the depth of the first well formed in the peripheral circuit region.

Inventors

• 👤 Takashi Kumagai

Bibliographic Details