US6459150B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electronic substrate having an aperture position through a substrate, conductive pads, and an insulating layer
Assignee: Industrial Technology Research Institute
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Filing: 2000-08-17
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Granted: 2002-10-01
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Expires: 2020-08-17
Abstract
Abstract A single-step bumping/bonding method for forming a semiconductor package of two electronic substrates electrically connected together by solder bumps. In the method, a first electronic substrate is provided equipped with a first plurality of conductive pads formed in an insulating material layer, the plurality of conductive pads each having an aperture formed therethrough for receiving a solder material when the first electronic substrate is positioned juxtaposed to a second electronic substrate equipped with a second plurality of conductive pads such that solder bumps may be formed bonding the first plurality of conductive pads to the second plurality of conductive pads. One of the two electronic substrates may be a silicon wafer, while the other may be a printed circuit board or a silicon wafer.
Inventors
- 👤 Enboa Wu
- 👤 Tsung-Yao Chu
- 👤 Hsin-Chien Huang
- 👤 Rong-Shen Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 17:56
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/021; H10W20/023; H10W20/0238; H10W20/0242; H10W20/20; H10W70/00; H10W70/60; H10W70/62; H10W70/63; H10W70/635; H10W72/00; H10W72/01; H10W72/012; H10W72/01251; H10W72/01255; H10W72/071; H10W72/072; H10W72/07231; H10W72/07234; H10W72/07236; H10W72/07251; H10W72/073; H10W72/07331; H10W72/20; H10W72/221; H10W72/251; H10W72/90; H10W72/921; H10W72/923; H10W72/941; H10W72/9415; H10W72/951; H10W72/952; H10W90/00; H10W90/701; H10W90/721; H10W90/724; H10W99/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
208 words
A semiconductor package of two electronic substrates electrically connected together by solder bumps comprising: a first electronic substrate having a first plurality of conductive pads formed on a first surface insulated from each other by a first insulating material layer, said first electronic substrate further having a first plurality of apertures through said substrate, said first plurality of conductive pads and said first insulating material layer with one aperture corresponds to each conductive pad wherein said first plurality of apertures each having a sidewall coated with an adhesion promoter that is not a part of the first plurality of conductive pads, a second electronic substrate having a second plurality of conductive pads formed on a second surface insulated from each other by a second insulating material layer, said first plurality being equal to or different than said second plurality, one of said first and second electronic substrates being a silicon wafer while the other being a printed circuit board (PCB), a first plurality of solder bumps mechanically and electrically connecting said first plurality of conductive pads to said second plurality of conductive pads, and wherein said first plurality of solder bumps each filling one of said first plurality of apertures to form a first plurality of conductive plugs.
Claim 2
Dependent Claim
208 words
A semiconductor package of two electronic substrates electrically connected together by solder bumps comprising: a first electronic substrate having a first plurality of conductive pads formed on a first surface insulated from each other by a first insulating material layer, said first electronic substrate further having a first plurality of apertures through said substrate, said first plurality of conductive pads and said first insulating material layer with one aperture corresponds to each conductive pad wherein said first plurality of apertures each having a sidewall coated with an adhesion promoter that is not a part of the first plurality of conductive pads, a second electronic substrate having a second plurality of conductive pads formed on a second surface insulated from each other by a second insulating material layer, said first plurality being equal to or different than said second plurality, one of said first and second electronic substrates being a silicon wafer while the other being a printed circuit board (PCB), a first plurality of solder bumps mechanically and electrically connecting said first plurality of conductive pads to said second plurality of conductive pads, and wherein said first plurality of solder bumps each filling one of said first plurality of apertures to form a first plurality of conductive plugs.
Claim 3
Dependent Claim
37 words
A semiconductor package of two electronic substrates electrically connected together by solder bumps according to claim 1 , wherein said first electronic substrate being a silicon wafer and said second electronic substrate being a printed circuit board.
Claim 4
Dependent Claim
37 words
A semiconductor package of two electronic substrates electrically connected together by solder bumps according to claim 1 , wherein said first electronic substrate being a printed circuit board and said second electronic substrate being a silicon wafer.
Claim 5
Dependent Claim
30 words
A semiconductor package of two electronic substrates electrically connected together by solder bumps according to claim 1 , wherein both of said first and second electronic substrates are silicon wafers.
Claim 6
Dependent Claim
44 words
A semiconductor package of two electronic substrates electrically connected together by solder bumps according to claim 1 , wherein said first electronic substrate being a silicon wafer and said first plurality of conductive pads further comprises a layer of under-bump-metallurgy (UBM) material on top.
Claim 7
Dependent Claim
37 words
A semiconductor package of two electronic substrates electrically connected together by solder bumps according to claim 1 , wherein said first electronic substrate being a silicon wafer and said first insulating material layer being a passivation layer.
Claim 8
Dependent Claim
38 words
A semiconductor package of two electronic substrates electrically connected together by solder bumps according to claim 1 , wherein said second electronic substrate being a printed circuit board and said second insulating material layer being a solder mask.
Claim 9
Dependent Claim
33 words
A semiconductor package of two electronic substrates electrically connected together by solder bumps according to claim 1 , wherein said first plurality of solder bumps being reflown into a plurality of solder balls.
Claim 10
Dependent Claim
37 words
A semiconductor package of two electronic substrates electrically connected together by solder bumps according to claim 1 , wherein said first plurality of solder bumps each having a height between about 50 μm and about 100 μm.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-09-30 | 2006-04-01 | 2006-10-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-09-30 | 2010-04-01 | 2010-10-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-09-30 | 2014-04-01 | 2014-10-01 | $7700.00 | Window Closed / Lapsed |