System and method for interactive implementation and testing of logic cores on a programmable logic device

Claim 2

A computer-implemented method for developing a circuit design for a programmable logic device, comprising: creating a library of one or more run-time parameterizable logic cores; implementing a selected one of the one or more logic cores in a first configuration bitstream responsive to a first command including parameters that specify the logic core and placement of the core on the programmable logic device; downloading the first bitstream to the programmable logic device; responsive to a second command, applying a clock signal to the programmable logic device; and reporting, after application of the clock signal, states of selected elements implemented by the logic core.

Claim 3

The method of claim 1 , wherein the second command includes a parameter that specifies a number of cycles by which the clock signal is advanced.

Claim 4

The method of claim 2 , wherein the states of the selected elements are reported after each clock cycle.

Claim 5

The method of claim 3 , further comprising reading back a readback configuration bitstream from the programmable gate array after each clock cycle.

Claim 6

The method of claim 4 , further comprising downloading a predefined configuration bitstream to the programmable logic device responsive to a third command, wherein the predefined configuration bitstream configures the programmable logic device in a known state.

Claim 7

The method of claim 1 , wherein the first bitstream is downloaded to the device responsive to the first command.

Claim 8

The method of claim 6 , wherein the states of selected elements are reported responsive to the second command.

Claim 9

The method of claim 1 , wherein the first bitstream is downloaded to the device responsive to a third command.

Claim 10

The method of claim 1 , wherein the states of selected elements are reported responsive to the second command.

Claim 11

The method of claim 1 , wherein the states of selected elements are reported responsive to a third command.

Claim 12

The method of claim 1 , further comprising: removing an implementation of the logic core from the first configuration bitstream responsive to a third command whereby a modified configuration bitstream is created, wherein the third command includes a parameter that references the logic core to be removed; and downloading the modified configuration bitstream to the programmable logic device.

Claim 13

The method of claim 11 , wherein the modified configuration bitstream is downloaded responsive to the third command.

Claim 14

The method of claim 11 , wherein the modified configuration bitstream is downloaded responsive to a fourth command.

Claim 15

The method of claim 1 , further comprising reading back a readback configuration bitstream from the programmable logic device and reporting states of selected elements that implement one or more logic cores responsive to a third command.

Claim 16

The method of claim 1 , further comprising receiving the first and second commands from a command line interface.

Claim 17

The method of claim 1 , further comprising reading the first and second commands from a script file.

Claim 18

The method of claim 1 , further comprising receiving the first and second commands from a graphical user interface.

Claim 19

The method of claim 1 , further comprising downloading an initial predefined configuration bitstream to the programmable logic device prior to implementing the logic core.

Claim 20

The method of claim 1 , wherein the placement parameter includes data identifying a row and a column of a configurable logic block of the programmable logic device.

Claim 21

The method of claim 1 , further comprising: constructing one or more logic core definitions using object-oriented classes; and implementing the selected logic core using a class associated with the selected logic core.

Claim 22

A computer-implemented method for developing a circuit design for a programmable logic device, comprising: creating a library of run-time parameterizable logic cores; supplying a first configuration bitstream; implementing selected ones of the logic cores in the first configuration bitstream, thereby creating a second configuration bitstream and downloading the second configuration bitstream to the programmable logic device responsive to a set of first commands that include parameters that specify the logic cores and placement of the cores on the programmable logic device; creating a list identifying the selected ones of the logic cores implemented in the second configuration bitstream and the parameters used to implement the logic cores; responsive to a second command, applying a clock signal to the programmable logic device and automatically reporting after application of the clock signal states of selected elements implemented by the selected logic cores; responsive to a third command that includes a parameter that references a logic core to be removed, removing from the list of logic cores the logic core referenced in the third command, implementing in the first configuration bitstream remaining logic cores identified in the list, thereby creating a third configuration bitstream, and thereafter downloading the third configuration bitstream to the programmable logic device.

Claim 23

A computer-implemented method for developing a circuit design for a programmable logic device, comprising: creating a library of run-time parameterizable logic cores; supplying a first configuration bitstream; implementing selected ones of the logic cores in the first configuration bitstream, thereby creating a second configuration bitstream and downloading the second configuration bitstream to the programmable logic device responsive to a set of first commands that include parameters that specify the logic cores and placement of the cores on the programmable logic device; creating a list identifying the selected ones of the logic cores implemented in the second configuration bitstream and the parameters used to implement the logic cores; responsive to a second command, applying a clock signal to the programmable logic device and automatically reporting after application of the clock signal states of selected elements implemented by the selected logic cores; responsive to a third command that includes a parameter that references a logic core to be removed, removing from the list of logic cores the logic core referenced in the third command, implementing in the first configuration bitstream remaining logic cores identified in the list, thereby creating a third configuration bitstream, and thereafter downloading the third configuration bitstream to the programmable logic device.

Claim 26

A computer-implemented method for developing a circuit design for a programmable logic device, comprising: creating a library of one or more run-time parameterizable logic cores; interactively entering a first command including parameters that specify one of the logic cores, placement of the logic core on the programmable logic device, and initial functionality of the logic core, wherein in response the one of the logic cores is implemented in a first configuration bitstream and the first bitstream is downloaded to the programmable logic device; interactively entering a second command, wherein in response a clock signal input to the programmable logic device is advanced and signal states of selected elements implemented by the logic core are automatically reported after advancing the clock; and interactively entering a third command including parameters that specify the one of the logic cores, placement of the logic core on the programmable logic device, and functionality of the logic core that is different from the initial functionality, wherein in response the one of the logic cores is implemented in a second configuration bitstream and the second bitstream is downloaded to the programmable logic device.

Claim 27

A computer-implemented method for developing a circuit design for a programmable logic device, comprising: creating a library of one or more run-time parameterizable logic cores; interactively entering a first command including parameters that specify one of the logic cores, placement of the logic core on the programmable logic device, and initial functionality of the logic core, wherein in response the one of the logic cores is implemented in a first configuration bitstream and the first bitstream is downloaded to the programmable logic device; interactively entering a second command, wherein in response a clock signal input to the programmable logic device is advanced and signal states of selected elements implemented by the logic core are automatically reported after advancing the clock; and interactively entering a third command including parameters that specify the one of the logic cores, placement of the logic core on the programmable logic device, and functionality of the logic core that is different from the initial functionality, wherein in response the one of the logic cores is implemented in a second configuration bitstream and the second bitstream is downloaded to the programmable logic device.

Claim 28

The method of claim 23 , further comprising interactively entering a fourth command including parameters that specify the one of the logic cores and placement on the programmable logic device, wherein in response the implementation of the one of the logic cores is removed from the second-configuration bitstream, thereby creating a third configuration bitstream, and the third configuration bitstream is thereafter downloaded to the programmable logic device.

Claim 31

The system of claim 25 , wherein the logic cores in the library are implemented as object oriented classes.

Claim 32

The system of claim 26 , wherein the object oriented classes are Java classes.