US6453410B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Computer system having a cache memory and a tracing function
Assignee: Renesas Electronics Corp
•
Filing: 1999-07-06
•
Granted: 2002-09-17
•
Expires: 2019-07-06
Abstract
Abstract A computer system operates for pipe-line processing, and includes a cache memory and a tracing circuit for tracing the operation of the pipe-line processor for developing the computer system. The pipe-line processing is executed in separate stage blocks, and the trace data are supplied to the tracing circuit through a dedicated tracing bus at the final stage of the pipe-line processing. If the data is hit in the cache memory, the trace data can be provided to the tracing circuit without losing real time processing.
Inventors
- 👤 Shuji Satoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:29
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3636; G06F11/364
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
136 words
A computer system comprising: a pipe-line processor for pipe-line processing of an instruction code in synchrony with a pipe-line clock signal, a system memory for storing data for said pipe-line processor, a system bus for transferring data between said pipe-line processor and said memory, a tracing circuit for storing trace data output from said pipe-line processor, and a trace data transfer circuit for transferring said trace data between said pipe-line processor and said tracing circuit independently of operation of said system bus, wherein said trace data transfer circuit transfers said trace data to said tracing circuit at a final stage of said pipe-line processing, and wherein said trace data transfer circuit comprises a mask signal generator for generating a mask signal for masking said pipe-line clock signal for a specified interval depending on said instruction code.
Claim 2
Dependent Claim
136 words
A computer system comprising: a pipe-line processor for pipe-line processing of an instruction code in synchrony with a pipe-line clock signal, a system memory for storing data for said pipe-line processor, a system bus for transferring data between said pipe-line processor and said memory, a tracing circuit for storing trace data output from said pipe-line processor, and a trace data transfer circuit for transferring said trace data between said pipe-line processor and said tracing circuit independently of operation of said system bus, wherein said trace data transfer circuit transfers said trace data to said tracing circuit at a final stage of said pipe-line processing, and wherein said trace data transfer circuit comprises a mask signal generator for generating a mask signal for masking said pipe-line clock signal for a specified interval depending on said instruction code.
Claim 3
Dependent Claim
35 words
The computer system as defined in claim 1 , wherein said tracing circuit repeatedly stores said trace data in a tracing memory at the same address when said mask signal masks said pipe-line clock signal.
Claim 4
Dependent Claim
34 words
The computer system as defined in claim 1 , wherein said pipe-line processing includes an instruction fetch stage, a register fetch stage, an execution stage, a data fetch stage, and a write back stage.
Claim 5
Dependent Claim
17 words
The computer system as defined in claim 1 , further comprising a data cache memory cache memory.
Claim 6
Dependent Claim
29 words
The computer system as defined in claim 1 , wherein said trace data transfer circuit includes a dedicated tracing bus for transferring said trace data to said tracing circuit.
Claim 7
Dependent Claim
69 words
The computer system as defined in claim 5 , wherein said trace data transfer circuit includes at least one group of cascaded latches for transferring one of said trace data in synchrony with said pipe-line clock signal, said cascaded latches include a first stage latch for latching data generated in a first stage of said pipe-line processing and a last stage latch for transferring data to said tracing bus.
Claim 8
Dependent Claim
49 words
The computer system as defined in claim 6 , wherein said at least one group includes a plurality of groups of cascaded latches, said final stage latches of said plurality of groups of cascaded latches outputting said trace data at the same clock pulse of said pipe-line clock signal.
Claim 9
Dependent Claim
15 words
The computer system as defined in claim 1 , further comprising an instruction cache memory.
Claim 10
Dependent Claim
20 words
The computer system as defined in claim 1 , further comprising a data cache memory and an instruction cache memory.
References Cited (Backward Citations)
US4674089A
Cited
JPS6383841A
Cited
JPH0251745A
Cited
JPH03137736A
Cited
JPH03256141A
Cited
JPH03263136A
Cited
JPH04296944A
Cited
JPH0683705A
Cited
JPH06161818A
Cited
US5379301A
Cited
US5564028A
Cited
JPH07271705A
Cited
JPH08171505A
Cited
JPH08335177A
Cited
US6055651A
Cited
JPH1011290A
Cited
US5751735A
Cited
JPH10240570A
Cited
US5933626A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-09-16 | 2006-03-18 | 2006-09-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-09-16 | 2010-03-18 | 2010-09-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-09-16 | 2014-03-18 | 2014-09-17 | $7700.00 | Window Closed / Lapsed |