Patent US6446248B1 successfully refreshed from Google Patents.
US6446248B1
Expired / Lapsed
US
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Spare cells placement methodology
Assignee: Bell Semiconductor LLC
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Filing: 2000-01-28
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Granted: 2002-09-03
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Expires: 2020-01-28
Abstract
Abstract Methods for designing an integrated circuit is disclosed. In the present invention, the integrated circuit is first created by placing and routing standard cells of the integrated circuit. After routing the standard cells, empty spaces unused by the standard cells are extracted. After extracting the unused areas, clusters of metal-programmable transistors are inserted into the unused areas by an area-based placement/routing tool to form “ponds” of gates (POGs). When design changes are desired after the formation of the integrated circuit, the metal-programmable transistors are programmed to form desired spare cells to implement the desired design changes by making changes to the upper layer masks for the integrated circuit.
Inventors
- 👤 Richard L. Solomon
- 👤 Paul J. Smith
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 12:30
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907; G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/392
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
56 words
A method of designing an integrated circuit having standard cells, the method comprising the steps of: partitioning the integrated circuit; placing the standard cells on the integrated circuit; routing the standard cells in accordance with a netlist; extracting empty spaces on the integrated circuit; and placing base cells including programmable transistors in the extracted empty spaces.
Claim 2
Independent Claim
56 words
A method of designing an integrated circuit having standard cells, the method comprising the steps of: partitioning the integrated circuit; placing the standard cells on the integrated circuit; routing the standard cells in accordance with a netlist; extracting empty spaces on the integrated circuit; and placing base cells including programmable transistors in the extracted empty spaces.
Claim 3
Dependent Claim
22 words
The method of claim 1 , further comprising the step of: determining a design change to be made to the integrated circuit.
Claim 4
Dependent Claim
25 words
The method of claim 2 , further comprising the step of: implementing the design change by programming the programmable transistors by interconnecting the programmable transistors.
Claim 5
Dependent Claim
32 words
The method of claim 3 , wherein the step of implementing the design change further includes the step of: interconnecting the programmed transistors to the standard cells to implement the design change.
Claim 6
Dependent Claim
29 words
The method of claim 4 , wherein the step of implementing the design change further includes the step of: making changes to upper layer masks of the integrated circuit.
Claim 7
Dependent Claim
26 words
The method of claim 3 , wherein programming the programmable transistors includes the step of adding traces to the integrated circuit to interconnect the programmable transistors.
Claim 8
Dependent Claim
20 words
The method of claim 3 , wherein the programmable transistors include metal-programmable transistors having a plurality of complimentary transistor pairs.
Claim 9
Dependent Claim
19 words
The method of claim 7 , wherein each complimentary transistor pair includes one-P type transistor and one N-type transistor.
Claim 10
Dependent Claim
22 words
The method claim 1 , wherein the step of placing the base cells is conducted by an area-based placement and routing tool.
Claim 11
Independent Claim
80 words
An apparatus for designing an integrated circuit having standard cells, said apparatus comprising: a processor for executing stored program instruction steps; and a memory connected to the processor for storing the program instruction steps, wherein the program instruction steps include: partitioning the integrated circuit; placing the standard cells on the integrated circuit; routing the standard cells in accordance with a netlist; extracting empty spaces on the integrated circuit; and placing base cells including programmable transistors in the extracted empty spaces.
Claim 12
Independent Claim
80 words
An apparatus for designing an integrated circuit having standard cells, said apparatus comprising: a processor for executing stored program instruction steps; and a memory connected to the processor for storing the program instruction steps, wherein the program instruction steps include: partitioning the integrated circuit; placing the standard cells on the integrated circuit; routing the standard cells in accordance with a netlist; extracting empty spaces on the integrated circuit; and placing base cells including programmable transistors in the extracted empty spaces.
Claim 13
Dependent Claim
24 words
The apparatus of claim 10 , wherein the program instruction steps further include: determining a design change to be made to the integrated circuit.
Claim 14
Dependent Claim
27 words
The apparatus of claim 11 , wherein the program instruction steps further include: implementing the design change by programming the programmable transistors by interconnecting the programmable transistors.
Claim 15
Dependent Claim
32 words
The apparatus of claim 12 , wherein the step of implementing the design change further includes the step of: interconnecting the programmed transistors to the standard cells to implement the design change.
Claim 16
Dependent Claim
29 words
The apparatus of claim 13 , wherein the step of implementing the design change further includes the step of: making changes to upper layer masks of the integrated circuit.
Claim 17
Dependent Claim
26 words
The apparatus of claim 12 , wherein programming the programmable transistors includes the step of adding traces to the integrated circuit to interconnect the programmable transistors.
Claim 18
Dependent Claim
20 words
The apparatus of claim 12 , wherein the programmable transistors include metal-programmable transistors having a plurality of complimentary transistor pairs.
Claim 19
Dependent Claim
65 words
An ECAD system for designing an integrated circuit having standard cells, said ECAD system comprising: means for partitioning the integrated circuit; means for placing the standard cells on the integrated circuit; means for routing the standard cells in accordance with a netlist; means for extracting empty spaces on the integrated circuit; and means for placing base cells including programmable transistors in the extracted empty spaces.
Claim 20
Dependent Claim
65 words
An ECAD system for designing an integrated circuit having standard cells, said ECAD system comprising: means for partitioning the integrated circuit; means for placing the standard cells on the integrated circuit; means for routing the standard cells in accordance with a netlist; means for extracting empty spaces on the integrated circuit; and means for placing base cells including programmable transistors in the extracted empty spaces.
Claim 21
Dependent Claim
21 words
The ECAD system for claim 17 further comprising: means for determining a design change to be made to the integrated circuit.
Claim 22
Dependent Claim
24 words
The ECAD system for claim 18 further comprising: means for implementing the design change by programming the programmable transistors by interconnecting the programmable transistors.
Claim 23
Dependent Claim
23 words
The ECAD system for claim 19 further comprising: means for interconnecting the programmed transistors to the standard cells to implement the design change.
Claim 24
Dependent Claim
21 words
The ECAD system for claim 20 , further comprising: means for making changes to upper layer masks of the integrated circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-09-02 | 2006-03-04 | 2006-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-09-02 | 2010-03-04 | 2010-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-09-02 | 2014-03-04 | 2014-09-03 | $7700.00 | Window Closed / Lapsed |