US6226775B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit designing method of an interconnection thereof and recording medium in which the method is recorded for empty area
Assignee: NEC Corp
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Filing: 1998-08-25
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Granted: 2001-05-01
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Expires: 2018-08-25
Abstract
Abstract At the time of the preparation of the core macro, the empty interconnection area extraction on the core macro is carried out and the fixed passage in the core macro is prepared by using the empty interconnection area. At the time of the chip layout, the interconnection is provided by using the interconnection for the fixed passage in the core macro. Also, at the time of the preparation of the core macro, the fixed passage interconnection in the core macro is set either in the VDD potential or in the GND potential to prepare the delay library of the core macro.
Inventors
- 👤 Tamotsu Yamada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 21:48
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/10; G; G06; G06F; G06F30/00; G06F30/30; G06F30/39
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
54 words
A method of designing an interconnection of a semiconductor integrated circuit including a core macro, said method comprising carrying out a core macro processing, said core macro processing comprising: extracting an empty area inside of said core macro; and creating a signal interconnection and its delay library with respect to the extracted empty area.
Claim 2
Independent Claim
54 words
A method of designing an interconnection of a semiconductor integrated circuit including a core macro, said method comprising carrying out a core macro processing, said core macro processing comprising: extracting an empty area inside of said core macro; and creating a signal interconnection and its delay library with respect to the extracted empty area.
Claim 3
Dependent Claim
43 words
A method according to claim 1 further comprising a chip layout processing, said chip layout processing comprising: connecting a signal interconnection which is created with respect to an empty area which is extracted in the core macro layout processing and the delay library.
Claim 4
Dependent Claim
20 words
A semiconductor integrated circuit in which an interconnection is determined in accordance with the method described in claim 2 .
Claim 5
Dependent Claim
22 words
A recording medium wherein a program is recorded for allowing a computer to carry out the method described in claim 2 .
Claim 6
Dependent Claim
20 words
A semiconductor integrated circuit in which an interconnection is determined in accordance with the method described in claim 1 .
Claim 7
Dependent Claim
22 words
A recording medium wherein a program is recorded for allowing a computer to carry out the method described in claim 1 .
Claim 8
Independent Claim
76 words
A method of designing an interconnection of a semiconductor integrated circuit including a core macro, said method comprising: processing a layout of a core macro on the basis of a net list which has been input; extracting an empty interconnection area from within the core macro which has been laid out; and processing a fixed passage interconnection inside the core macro and creating the interconnection by using the empty interconnection area as a signal interconnection area.
Claim 9
Independent Claim
76 words
A method of designing an interconnection of a semiconductor integrated circuit including a core macro, said method comprising: processing a layout of a core macro on the basis of a net list which has been input; extracting an empty interconnection area from within the core macro which has been laid out; and processing a fixed passage interconnection inside the core macro and creating the interconnection by using the empty interconnection area as a signal interconnection area.
Claim 10
Dependent Claim
93 words
A method of designing an interconnection of a semiconductor integrated circuit according to claim 7 , the method comprising: creating a delay library in which a delay characteristic is described with respect to the core macro in which the interconnection is prepared in the fixed passage interconnection processing inside of the core macro; providing a terminal for the passage interconnection with respect to the interconnection which has been prepared; and referring to the delay library and preparing a floor plan and an automatic layout by using the terminal and performing the signal interconnection.
Claim 11
Dependent Claim
20 words
A semiconductor integrated circuit in which an interconnection is determined in accordance with the method described in claim 8 .
Claim 12
Dependent Claim
22 words
A recording medium wherein a program is recorded for allowing a computer to carry out the method described in claim 8 .
Claim 13
Dependent Claim
20 words
A semiconductor integrated circuit in which an interconnection is determined in accordance with the method described in claim 7 .
Claim 14
Dependent Claim
22 words
A recording medium wherein a program is recorded for allowing a computer to carry out the method described in claim 7 .
References Cited (Backward Citations)
JPH0461275A
Cited
JPH05109892A
Cited
JPH06244387A
Cited
JPH06326190A
Cited
JPH0737987A
Cited
US6002857A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-04-30 | 2004-10-30 | 2005-05-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-04-30 | 2008-10-30 | 2009-05-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-04-30 | 2012-10-30 | 2013-05-01 | $7700.00 | Window Closed / Lapsed |