Patent US6444548B2 successfully refreshed from Google Patents.
US6444548B2
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Bitline diffusion with halo for improved array threshold voltage control
Assignee: GlobalFoundries Inc
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Filing: 1999-02-25
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Granted: 2002-09-03
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Expires: 2019-02-25
Abstract
Abstract A integrated circuit device and method for manufacturing an integrated circuit device includes forming a patterned gate stack, adjacent a storage device, to include a storage node diffusion region adjacent the storage device and a bitline contact diffusion region opposite the storage node diffusion region, implanting an impurity in the storage node diffusion region and the bitline contact diffusion region, forming an insulator layer over the patterned gate stack, removing a portion of the insulator layer from the bitline contact diffusion region to form sidewall spacers along a portion of the patterned gate stack adjacent the bitline contact diffusion region, implanting a halo implant into the bitline contact diffusion region, wherein the insulator layer is free from blocking the halo implant from the second diffusion region and annealing the integrated circuit device to drive the halo implant ahead of the impurity.
Inventors
- 👤 Ramachandra Divakaruni
- 👤 Yujun Li
- 👤 Jack A. Mandelman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 05:46
CPC Classifications
H; H10; H10D; H10D99/00; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10D30/00; H10D30/01; H10D30/021; H10D30/0218; H10D30/022; H10P; H10P30/00; H10P30/20; H10P30/22; H10P30/221; H10P30/222; H10B12/30; H10B12/48; H10B12/485
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
92 words
A method for manufacturing an integrated circuit device, said method comprising: providing a substrate including a deep trench capacitor and a patterned gate stack; implanting a first type impurity to form a first diffusion region on a first side of said patterned gate stack and a second diffusion region on a second side of said patterned gate stack; forming a patterned insulator over said patterned gate stack, said patterned insulator exposing said second diffusion region; and implanting a second type impurity to form an angled halo implant in said second diffusion region.
Claim 2
Independent Claim
92 words
A method for manufacturing an integrated circuit device, said method comprising: providing a substrate including a deep trench capacitor and a patterned gate stack; implanting a first type impurity to form a first diffusion region on a first side of said patterned gate stack and a second diffusion region on a second side of said patterned gate stack; forming a patterned insulator over said patterned gate stack, said patterned insulator exposing said second diffusion region; and implanting a second type impurity to form an angled halo implant in said second diffusion region.
Claim 3
Dependent Claim
111 words
The method in claim 1 , wherein said implanting a first type impurity comprises: patterning a first mask to expose a first substrate region on said first side of said patterned gate stack; implanting a first species of said first type impurity into said first substrate region to form said first diffusion region using a first doping concentration; removing said first mask; patterning a second mask to expose a second substrate region on said second side of said patterned gate stack; implanting a second species of said first type impurity into said second substrate region to form said second diffusion region using a second doping concentration; and removing said second mask.
Claim 4
Dependent Claim
18 words
The method in claim 2 , wherein said second doping concentration is higher than said first doping concentration.
Claim 5
Dependent Claim
19 words
The method in claim 3 , wherein said second doping concentration is approximately 10 times said first doping concentration.
Claim 6
Dependent Claim
67 words
The method in claim 1 , wherein said implanting a second type impurity to form said angled halo implant comprises an angled ion implantation and a geometry of said patterned gate stack, said patterned insulator and said second diffusion region allows ions applied at an angle up to approximately 30° to the normal of a surface of said second diffusion region to reach said second diffusion region.
Claim 7
Dependent Claim
28 words
The method in claim 1 , further comprising, after said forming of said patterned insulator, introducing an amount of a first type impurity in said second diffusion region.
Claim 8
Dependent Claim
32 words
The method in claim 6 , wherein said patterned gate stack, said first diffusion region and said second diffusion region are formed in an array area comprising dynamic random access memory cells.
Claim 9
Dependent Claim
41 words
The method in claim 7 , further comprising forming support devices in a support area, wherein said introducing an amount of a first type impurity further includes introducing said first type impurity into source and drain regions of said support devices.
Claim 10
Dependent Claim
31 words
The method in claim 8 , wherein said implanting a second type impurity to form a halo implant includes implanting selected ones of said support devices with said second type impurity.
Claim 11
Dependent Claim
54 words
The method in claim 9 , further comprising: forming a patterned insulator over said patterned gate stack and said support devices, said patterned insulator including bitline contact openings, support source openings and support drain openings; and simultaneously depositing a conductor into said bitline contact openings, said support source openings and said support drain openings.
Claim 12
Dependent Claim
11 words
The method in claim 10 , wherein said conductor comprises tungsten.
Claim 13
Dependent Claim
23 words
The method in claim 1 , wherein said patterned insulator is free from blocking said second type impurity from said second diffusion region.
Claim 14
Dependent Claim
25 words
The method in claim 1 , further comprising annealing said integrated circuit device to drive said second type impurity ahead of said first type impurity.
Claim 15
Dependent Claim
13 words
The method in claim 13 , wherein said annealing comprises a furnace anneal.
Claim 16
Dependent Claim
20 words
The method in claim 13 , wherein said annealing comprises a rapid thermal anneal to freeze said angled halo implant.
Claim 17
Dependent Claim
32 words
The method in claim 1 , wherein said patterned gate stack, said first diffusion region and said second diffusion region are formed in an array area comprising dynamic random access memory cells.
Claim 18
Dependent Claim
40 words
The method in claim 16 , further comprising forming support devices in a support area, wherein said implanting a first type impurity includes implanting a species of said first type impurity into source and drain regions of said support devices.
Claim 19
Dependent Claim
40 words
The method in claim 16 , further comprising forming support devices in a support area, wherein said implanting a second type impurity to form said halo implant includes implanting selected ones of said support devices with said second type impurity.
Claim 20
Dependent Claim
56 words
The method in claim 18 , further comprising: forming a second patterned insulator over said patterned gate stack and said support devices, said second patterned insulator including bitline contact openings, support source openings and support drain openings; and simultaneously depositing a conductor into said bitline contact openings, said support source openings and said support drain openings.
Claim 21
Dependent Claim
11 words
The method in claim 19 , wherein said conductor comprises tungsten.
Claim 22
Independent Claim
160 words
A method for manufacturing an integrated circuit device, said method comprising: providing a substrate including a deep trench capacitor and a patterned gate stack having a first side and a second side; patterning a first mask to expose a first substrate region on said first side of said patterned gate stack; implanting a first species of a first type impurity into said first substrate region to form said first diffusion region using a first doping concentration; removing said first mask; patterning a second mask to expose a second substrate region on said second side of said patterned gate stack; implanting a second species of said first type impurity having a first conductivity into said second substrate region to form said second diffusion region using a second doping concentration, wherein said second doping concentration is higher than said first doping concentration; removing said second mask; and implanting a second type impurity to form a halo implant into said second diffusion region.
Claim 23
Independent Claim
160 words
A method for manufacturing an integrated circuit device, said method comprising: providing a substrate including a deep trench capacitor and a patterned gate stack having a first side and a second side; patterning a first mask to expose a first substrate region on said first side of said patterned gate stack; implanting a first species of a first type impurity into said first substrate region to form said first diffusion region using a first doping concentration; removing said first mask; patterning a second mask to expose a second substrate region on said second side of said patterned gate stack; implanting a second species of said first type impurity having a first conductivity into said second substrate region to form said second diffusion region using a second doping concentration, wherein said second doping concentration is higher than said first doping concentration; removing said second mask; and implanting a second type impurity to form a halo implant into said second diffusion region.
Claim 24
Dependent Claim
90 words
The method in claim 21 , wherein said implanting a second type impurity to form a halo implant comprises: forming an insulator over said patterned gate stack; and removing a portion of said insulator from said second diffusion region to form a sidewall spacer along a portion of said patterned gate stack adjacent said second diffusion region, wherein said implanting a second type impurity comprises an angled ion implantation into said second diffusion region, wherein said insulator is free from blocking said angled ion implantation from said second diffusion region.
Claim 25
Dependent Claim
19 words
The method in claim 21 , wherein said second doping concentration is approximately 10 times said first doping concentration.
Claim 26
Dependent Claim
60 words
The method in claim 21 , wherein said implanting a second type impurity comprises an angled ion implantation and a geometry of said patterned gate stack, said insulator and said second diffusion region allows ions applied at an angle up to approximately 30° to the normal of a surface of said second diffusion region to reach said second diffusion region.
Claim 27
Dependent Claim
32 words
The method in claim 21 , wherein said patterned gate stack, said first diffusion region and said second diffusion region are formed in an array area comprising dynamic random access memory cells.
Claim 28
Dependent Claim
43 words
The method in claim 25 , further comprising forming support devices in a support area, wherein said implanting a first species of a first type impurity includes implanting said first species into source and drain regions of selected ones of said support devices.
Claim 29
Dependent Claim
43 words
The method in claim 25 , further comprising forming support devices in a support area, wherein said implanting a second species of a first type impurity includes implanting said second species into source and drain regions of selected ones of said support devices.
Claim 30
Dependent Claim
54 words
The method in claim 27 , further comprising: forming a patterned insulator over said patterned gate stack and said support devices, said patterned insulator including bitline contact openings, support source openings and support drain openings; and simultaneously depositing a conductor into said bitline contact openings, said support source openings and said support drain openings.
Claim 31
Dependent Claim
25 words
The method in claim 21 , further comprising annealing said integrated circuit device to drive said second type impurity ahead of said first type impurity.
References Cited (Backward Citations)
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