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US6438735B1
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Methods and apparatuses for designing integrated circuits
Assignee: Synopsys Inc
•
Filing: 1999-05-17
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Granted: 2002-08-20
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Expires: 2019-05-17
Abstract
Abstract Methods and apparatuses for designing a plurality of integrated circuits (ICs) from a language representation of hardware. In one example of a method, a technology independent RTL (register transfer level) netlist is partitioned between representations of a plurality of ICs. In a typical example of the method, a hardware description language (HDL) code is written and compiled without regard to splitting the design among multiple ICs. After compilation, a partition of the technology independent RTL netlist, obtained from the compilation, is performed among the multiple ICs. After a partition, the technology independent RTL netlist is mapped to a particular target technology (e.g. a particular IC vendor's architecture for implementing logic circuitry), and place and route tools may be used to create the design in multiple ICs (e.g. field programmable gate arrays). In an example of another method, an HDL code is compiled to produce an RTL netlist representation which specifies a plurality of ICs in which logic, designed for placement on one of the plurality of ICs, is replicated for placement on another one of the plurality of ICs. In a typical example of this method, the HDL code is written and compiled without regard to splitting the design among multiple ICs and a partition operation is performed on the RTL netlist from the results of the compiled HDL code. The partition operation produces multiple ICs and selected logic may then be replicated on the multiple ICs. In an example of another method, an HDL code is compiled to produce an RTL netlist representation which includes at least one RTL component. The one RTL component is split into multiple RTL components, each of which is designed for placement on a separate IC.
Inventors
- 👤 Kenneth S. McElvain
- 👤 Robert Erickson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 10:42
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/323; G06F30/327; G06F30/39; G06F30/392
Claims Analysis
Total Claims: 112
Claim 1
Independent Claim
27 words
A method of designing a plurality of integrated circuits (ICs), said method comprising: partitioning a technology independent RTL (register transfer level) netlist between said plurality of ICs.
Claim 2
Independent Claim
27 words
A method of designing a plurality of integrated circuits (ICs), said method comprising: partitioning a technology independent RTL (register transfer level) netlist between said plurality of ICs.
Claim 3
Dependent Claim
28 words
A method as in claim 1 further comprising: compiling a hardware description language (HDL) code, wherein said technology independent RTL netlist is produced after compiling said HDL code.
Claim 4
Dependent Claim
36 words
A method as in claim 2 wherein said ICs each comprise a programmable logic device and wherein said partitioning comprises assigning a portion of said technology independent RTL netlist to one of said plurality of ICs.
Claim 5
Dependent Claim
19 words
A method as in claim 2 further comprising: mapping said technology independent RTL netlist to a selected technology architecture.
Claim 6
Dependent Claim
14 words
A method as in claim 4 wherein said mapping is performed after said partitioning.
Claim 7
Dependent Claim
26 words
A method as in claim 4 further comprising: performing a place and route operation after said mapping to implement said ICs in said selected technology architecture.
Claim 8
Dependent Claim
19 words
A method as in claim 4 further comprising: optimizing a design of each of said ICs after said partitioning.
Claim 9
Dependent Claim
20 words
A method as in claim 7 wherein said optimizing optimizes each of said ICs by removing duplicative logic or input/outputs.
Claim 10
Dependent Claim
17 words
A method as in claim 4 wherein said HDL code is created without regard to said partitioning.
Claim 11
Dependent Claim
17 words
A method as in claim 7 wherein said optimizing and said mapping are performed after said partitioning.
Claim 12
Dependent Claim
46 words
A method as in claim 4 further comprising: mapping portions of said technology independent RTL netlist to a selected technology architecture wherein estimates of IC resources are obtained from said mapping portions and wherein said mapping portions is performed after said compiling and before said mapping.
Claim 13
Dependent Claim
21 words
A method as in claim 4 further comprising: optimizing interconnects between modules of said technology independent RTL netlist before said partitioning.
Claim 14
Dependent Claim
18 words
A method as in claim 11 wherein said estimates are used to decide how to perform said partitioning.
Claim 15
Dependent Claim
23 words
A method as in claim 13 wherein a user considers said estimates and selects a command to decide how to perform said partitioning.
Claim 16
Dependent Claim
47 words
A method as in claim 4 wherein said ICs each comprise a programmable logic device and wherein said method further comprises: testing a prototype of a system with said ICs; performing a synthesis of said HDL code to generate at least one Application Specific Integrated Circuit (ASIC).
Claim 17
Dependent Claim
52 words
A machine readable medium containing a plurality of executable instructions, which when executed on a digital processing system cause said digital processing system to perform a method of designing a plurality of integrated circuits (ICs), said method comprising: partitioning a technology independent RTL (register transfer level) netlist between said plurality of ICs.
Claim 18
Dependent Claim
52 words
A machine readable medium containing a plurality of executable instructions, which when executed on a digital processing system cause said digital processing system to perform a method of designing a plurality of integrated circuits (ICs), said method comprising: partitioning a technology independent RTL (register transfer level) netlist between said plurality of ICs.
Claim 19
Dependent Claim
34 words
A machine readable medium as in claim 16 , wherein said method further comprises: compiling a hardware description language (HDL) code, wherein said technology independent RTL netlist is produced after compiling said HDL code.
Claim 20
Dependent Claim
17 words
A machine readable medium as in claim 17 wherein said ICs each comprise a programmable logic device.
Claim 21
Dependent Claim
25 words
A machine readable medium as in claim 17 , wherein said method further comprises: mapping said technology independent RTL netlist to a selected technology architecture.
Claim 22
Dependent Claim
16 words
A machine readable medium as in claim 19 wherein said mapping is performed after said partitioning.
Claim 23
Dependent Claim
32 words
A machine readable medium as in claim 19 , wherein said method further comprises: performing a place and route operation after said mapping to implement said ICs in said selected technology architecture.
Claim 24
Dependent Claim
25 words
A machine readable medium as in claim 19 , wherein said method further comprises: optimizing a design of each of said ICs after said partitioning.
Claim 25
Dependent Claim
22 words
A machine readable medium as in claim 22 wherein said optimizing optimizes each of said ICs by removing duplicative logic or input/outputs.
Claim 26
Dependent Claim
19 words
A machine readable medium as in claim 19 wherein said HDL code is created without regard to said partitioning.
Claim 27
Dependent Claim
19 words
A machine readable medium as in claim 22 wherein said optimizing and said mapping are performed after said partitioning.
Claim 28
Dependent Claim
52 words
A machine readable medium as in claim 19 , wherein said method further comprises: mapping portions of said technology independent RTL netlist to a selected technology architecture wherein estimates of IC resources are obtained from said mapping portions and wherein said mapping portions is performed after said compiling and before said mapping.
Claim 29
Dependent Claim
27 words
A machine readable medium as in claim 19 , wherein said method further comprises: optimizing interconnects between modules of said technology independent RTL netlist before said partitioning.
Claim 30
Dependent Claim
20 words
A machine readable medium as in claim 26 wherein said estimates are used to decide how to perform said partitioning.
Claim 31
Dependent Claim
25 words
A machine readable medium as in claim 28 wherein a user considers said estimates and selects a command to decide how to perform said partitioning.
Claim 32
Dependent Claim
49 words
A machine readable medium as in claim 19 wherein said ICs each comprise a programmable logic device and wherein said method further comprises: testing a prototype of a system with said ICs; performing a synthesis of said HDL code to generate at least one Application Specific Integrated Circuit (ASIC).
Claim 33
Independent Claim
58 words
A method of designing a plurality of integrated circuits (ICs), said method comprising: compiling a hardware description language (HDL) code to produce an RTL netlist representation which specifies said plurality of ICs; selecting logic designed for placement on one of said plurality of ICs and replicating said logic for placement on another one of said plurality of ICs.
Claim 34
Independent Claim
58 words
A method of designing a plurality of integrated circuits (ICs), said method comprising: compiling a hardware description language (HDL) code to produce an RTL netlist representation which specifies said plurality of ICs; selecting logic designed for placement on one of said plurality of ICs and replicating said logic for placement on another one of said plurality of ICs.
Claim 35
Dependent Claim
19 words
A method as in claim 31 further comprising: partitioning said RTL netlist representation to specify said plurality of ICs.
Claim 36
Dependent Claim
26 words
A method as in claim 32 further comprising: mapping said RTL netlist representation to a selected technology architecture, wherein said RTL netlist representation is technology independent.
Claim 37
Dependent Claim
18 words
A method as in claim 33 wherein each of said plurality of ICs comprises a programmable logic device.
Claim 38
Dependent Claim
14 words
A method as in claim 33 wherein said mapping is performed after said partitioning.
Claim 39
Dependent Claim
25 words
A method as in claim 35 further comprising: performing a place and route operation after said mapping to implement logic in said plurality of ICs.
Claim 40
Dependent Claim
21 words
A method as in claim 36 further comprising: optimizing a design of each of said plurality of ICs after said partitioning.
Claim 41
Dependent Claim
18 words
A method as in claim 31 wherein said HDL code is created without specifying a plurality of ICs.
Claim 42
Dependent Claim
45 words
A method as in claim 33 further comprising: mapping portions of said RTL netlist representation to said selected technology architecture wherein estimates of IC resources are obtained from said mapping portions and wherein said mapping portions is performed after said compiling and before said mapping.
Claim 43
Dependent Claim
20 words
A method as in claim 39 wherein said estimates are used to decide how to perform said selecting and replicating.
Claim 44
Dependent Claim
39 words
A method as in claim 34 further comprising: testing a prototype of a system with said plurality of ICs; performing, after said testing, a synthesis on said HDL code to generate at least one Application Specific Integrated Circuit (ASIC).
Claim 45
Dependent Claim
83 words
A machine readable medium containing a plurality of executable instructions, which when executed on a digital processing system cause said digital processing system to perform a method of designing a plurality of integrated circuits (ICs), said method comprising: compiling a hardware description language (HDL) code to produce an RTL netlist representation which specifies said plurality of ICs; selecting logic designed for placement on one of said plurality of ICs and replicating said logic for placement on another one of said plurality of ICs.
Claim 46
Dependent Claim
83 words
A machine readable medium containing a plurality of executable instructions, which when executed on a digital processing system cause said digital processing system to perform a method of designing a plurality of integrated circuits (ICs), said method comprising: compiling a hardware description language (HDL) code to produce an RTL netlist representation which specifies said plurality of ICs; selecting logic designed for placement on one of said plurality of ICs and replicating said logic for placement on another one of said plurality of ICs.
Claim 47
Dependent Claim
24 words
A machine readable medium as in claim 42 , said method further comprising: partitioning said RTL netlist representation to specify said plurality of ICs.
Claim 48
Dependent Claim
31 words
A machine readable medium as in claim 43 , said method further comprising: mapping said RTL netlist representation to a selected technology architecture, wherein said RTL netlist representation is technology independent.
Claim 49
Dependent Claim
21 words
A machine readable medium as in claim 44 , wherein each of said plurality of ICs comprises a programmable logic device.
Claim 50
Dependent Claim
17 words
A machine readable medium as in claim 44 , wherein said mapping is performed after said partitioning.
Claim 51
Dependent Claim
30 words
A machine readable medium as in claim 46 , said method further comprising: performing a place and route operation after said mapping to implement logic in said plurality of ICs.
Claim 52
Dependent Claim
26 words
A machine readable medium as in claim 47 , said method further comprising: optimizing a design of each of said plurality of ICs after said partitioning.
Claim 53
Dependent Claim
20 words
A machine readable medium as in claim 42 wherein said HDL code is created without specifying a plurality of ICs.
Claim 54
Dependent Claim
50 words
A machine readable medium as in claim 44 , said method further comprising: mapping portions of said RTL netlist representation to said selected technology architecture wherein estimates of IC resources are obtained from said mapping portions and wherein said mapping portions is performed after said compiling and before said mapping.
Claim 55
Dependent Claim
22 words
A machine readable medium as in claim 50 wherein said estimates are used to decide how to perform said selecting and replicating.
Claim 56
Dependent Claim
44 words
A machine readable medium as in claim 45 , said method further comprising: testing a prototype of a system with said plurality of ICs; performing, after said testing, a synthesis on said HDL code to generate at least one Application Specific Integrated Circuit (ASIC).
Claim 57
Independent Claim
65 words
A method of designing a plurality of integrated circuits (ICs), said method comprising: compiling a hardware description language (HDL) code to produce an RTL netlist representation; selecting one RTL component in said RTL netlist representation and splitting said one RTL component into a first RTL component designed for placement on a first IC and a second RTL component designed for placement on a second IC.
Claim 58
Independent Claim
65 words
A method of designing a plurality of integrated circuits (ICs), said method comprising: compiling a hardware description language (HDL) code to produce an RTL netlist representation; selecting one RTL component in said RTL netlist representation and splitting said one RTL component into a first RTL component designed for placement on a first IC and a second RTL component designed for placement on a second IC.
Claim 59
Dependent Claim
22 words
A method as in claim 53 further comprising: partitioning said RTL netlist representation to specify said first IC and said second IC.
Claim 60
Dependent Claim
26 words
A method as in claim 54 further comprising: mapping said RTL netlist representation to a selected technology architecture, wherein said RTL netlist representation is technology independent.
Claim 61
Dependent Claim
21 words
A method as in claim 55 wherein each of said first IC and said second IC comprises a programmable logic device.
Claim 62
Dependent Claim
14 words
A method as in claim 55 wherein said mapping is performed after said partitioning.
Claim 63
Dependent Claim
46 words
A method as in claim 57 further comprising: performing a place and route operation after said mapping to implement logic for said first RTL component for placement on said first IC and to implement logic for said second RTL component for placement on said second IC.
Claim 64
Dependent Claim
20 words
A method as in claim 55 wherein said one RTL component is created as a unitary object after said compiling.
Claim 65
Dependent Claim
30 words
A method as in claim 55 wherein said one RTL component is a large RTL component having more inputs/outputs than is available on said first IC or said second IC.
Claim 66
Dependent Claim
45 words
A method as in claim 55 further comprising: mapping portions of said RTL netlist representation to said selected technology architecture wherein estimates of IC resources are obtained from said mapping portions and wherein said mapping portions is performed after said compiling and before said mapping.
Claim 67
Dependent Claim
21 words
A method as in claim 61 wherein said selecting and said splitting are performed after said compiling and before said mapping.
Claim 68
Dependent Claim
20 words
A method as in claim 62 wherein said estimates are used to determine how to split said, one RTL component.
Claim 69
Dependent Claim
90 words
A machine readable medium containing a plurality of executable instructions, which when executed on a digital processing system cause said digital processing system to perform a method of designing a plurality of integrated circuits (ICs), said method comprising: compiling a hardware description language (HDL) code to produce an RTL netlist representation; selecting one RTL component in said RTL netlist representation and splitting said one RTL component into a first RTL component designed for placement on a first IC and a second RTL component designed for placement on a second IC.
Claim 70
Dependent Claim
90 words
A machine readable medium containing a plurality of executable instructions, which when executed on a digital processing system cause said digital processing system to perform a method of designing a plurality of integrated circuits (ICs), said method comprising: compiling a hardware description language (HDL) code to produce an RTL netlist representation; selecting one RTL component in said RTL netlist representation and splitting said one RTL component into a first RTL component designed for placement on a first IC and a second RTL component designed for placement on a second IC.
Claim 71
Dependent Claim
28 words
A machine readable medium as in claim 64 , wherein said method further comprises: partitioning said RTL netlist representation to specify said first IC and said second IC.
Claim 72
Dependent Claim
32 words
A machine readable medium as in claim 65 , wherein said method further comprises: mapping said RTL netlist representation to a selected technology architecture, wherein said RTL netlist representation is technology independent.
Claim 73
Dependent Claim
23 words
A machine readable medium as in claim 66 wherein each of said first IC and said second IC comprises a programmable logic device.
Claim 74
Dependent Claim
16 words
A machine readable medium as in claim 66 wherein said mapping is performed after said partitioning.
Claim 75
Dependent Claim
52 words
A machine readable medium as in claim 68 , wherein said method further comprises: performing a place and route operation after said mapping to implement logic for said first RTL component for placement on said first IC and to implement logic for said second RTL component for placement on said second IC.
Claim 76
Dependent Claim
22 words
A machine readable medium as in claim 66 wherein said one RTL component is created as a unitary object after said compiling.
Claim 77
Dependent Claim
32 words
A machine readable medium as in claim 66 wherein said one RTL component is a large RTL component having more inputs/outputs than is available on said first IC or said second IC.
Claim 78
Dependent Claim
51 words
A machine readable medium as in claim 66 , wherein said method further comprises: mapping portions of said RTL netlist representation to said selected technology architecture wherein estimates of IC resources are obtained from said mapping portions and wherein said mapping portions is performed after said compiling and before said mapping.
Claim 79
Dependent Claim
23 words
A machine readable medium as in claim 72 wherein said selecting and said splitting are performed after said compiling and before said mapping.
Claim 80
Dependent Claim
22 words
A machine readable medium as in claim 73 wherein said estimates are used to determine how to split said one RTL component.
Claim 81
Independent Claim
56 words
A method of designing a plurality of integrated circuits (ICs), said method comprising: assigning a first portion of a technology independent RTL (register transfer level) netlist for placement on a first IC of said plurality of ICs; assigning a second portion of said technology independent RTL netlist to a second IC of said plurality of ICs.
Claim 82
Independent Claim
56 words
A method of designing a plurality of integrated circuits (ICs), said method comprising: assigning a first portion of a technology independent RTL (register transfer level) netlist for placement on a first IC of said plurality of ICs; assigning a second portion of said technology independent RTL netlist to a second IC of said plurality of ICs.
Claim 83
Dependent Claim
29 words
A method as in claim 75 further comprising: compiling a hardware description language (H DL) code, wherein said technology independent RTL netlist is produced after compiling said HDL code.
Claim 84
Dependent Claim
15 words
A method as in claim 76 wherein said ICs each comprise a programmable logic device.
Claim 85
Dependent Claim
19 words
A method as in claim 76 further comprising: mapping said technology independent RTL netlist to a selected technology architecture.
Claim 86
Dependent Claim
14 words
A method as in claim 78 wherein said mapping is performed after said assigning.
Claim 87
Dependent Claim
26 words
A method as in claim 78 further comprising: performing a place and route operation after said mapping to implement said ICs in said selected technology architecture.
Claim 88
Dependent Claim
19 words
A method as in claim 78 further comprising: optimizing a design of each of said ICs after said assigning.
Claim 89
Dependent Claim
20 words
A method as in claim 81 wherein said optimizing optimizes each of said ICs by removing duplicative logic or input/outputs.
Claim 90
Dependent Claim
17 words
A method as in claim 78 wherein said HDL code is created without regard to said assigning.
Claim 91
Dependent Claim
18 words
A method a s in claim 81 wherein said optimizing and said mapping are performed after said assigning.
Claim 92
Dependent Claim
46 words
A method as in claim 78 further comprising: mapping portions of said technology independent RTL netlist to a selected technology architecture wherein estimates of IC resources are obtained from said mapping portions and wherein said mapping portions is performed after said compiling and before said mapping.
Claim 93
Dependent Claim
21 words
A method as in claim 78 further comprising: optimizing interconnects between modules of said technology independent RTL netlist before said assigning.
Claim 94
Dependent Claim
18 words
A method as in claim 85 wherein said estimates are used to decide how to perform said assigning.
Claim 95
Dependent Claim
23 words
A method as in claim 87 wherein a user considers said estimates and selects a command to decide how to perform said assigning.
Claim 96
Dependent Claim
47 words
A method as in claim 78 wherein said ICs each comprise a programmable logic device and wherein said method further comprises: testing a prototype of a system with said ICs; performing a synthesis of said HDL code to generate at least one Application Specific Integrated Circuit (ASIC).
Claim 97
Dependent Claim
81 words
A machine readable medium containing a plurality of executable instructions, which when executed on a digital processing system cause said digital processing system to perform a method of designing a plurality of integrated circuits (ICs), said method comprising: assigning a first portion of a technology independent RTL (register transfer level) netlist for placement on a first IC of said plurality of ICs; assigning a second portion of said technology independent RTL netlist to a second IC of said plurality of ICs.
Claim 98
Dependent Claim
81 words
A machine readable medium containing a plurality of executable instructions, which when executed on a digital processing system cause said digital processing system to perform a method of designing a plurality of integrated circuits (ICs), said method comprising: assigning a first portion of a technology independent RTL (register transfer level) netlist for placement on a first IC of said plurality of ICs; assigning a second portion of said technology independent RTL netlist to a second IC of said plurality of ICs.
Claim 99
Dependent Claim
33 words
A machine readable medium as in claim 90 wherein said method further comprises: compiling a hardware description language (HDL) code, wherein said technology independent RTL netlist is produced after compiling said HDL code.
Claim 100
Dependent Claim
17 words
A machine readable medium as in claim 91 wherein said ICs each comprise a programmable logic device.
Claim 101
Dependent Claim
24 words
A machine readable medium as in claim 91 wherein said method further comprises: mapping said technology independent RTL netlist to a selected technology architecture.
Claim 102
Dependent Claim
16 words
A machine readable medium as in claim 93 wherein said mapping is performed after said assigning.
Claim 103
Dependent Claim
31 words
A machine readable medium as in claim 93 wherein said method further comprises: performing a place and route operation after said mapping to implement said ICs in said selected technology architecture.
Claim 104
Dependent Claim
24 words
A machine readable medium as in claim 93 wherein said method further comprises: optimizing a design of each of said ICs after said assigning.
Claim 105
Dependent Claim
22 words
A machine readable medium as in claim 96 wherein said optimizing optimizes each of said ICs by removing duplicative logic or input/outputs.
Claim 106
Dependent Claim
19 words
A machine readable medium as in claim 93 wherein said HDL code is created without regard to said assigning.
Claim 107
Dependent Claim
19 words
A machine readable medium as in claim 96 wherein said optimizing and said mapping are performed after said assigning.
Claim 108
Dependent Claim
51 words
A machine readable medium as in claim 93 wherein said method further comprises: mapping portions of said technology independent RTL netlist to a selected technology architecture wherein estimates of IC resources are obtained from said mapping portions and wherein said mapping portions is performed after said compiling and before said mapping.
Claim 109
Dependent Claim
26 words
A machine readable medium as in claim 93 wherein said method further comprises: optimizing interconnects between modules of said technology independent RTL netlist before said assigning.
Claim 110
Dependent Claim
20 words
A machine readable medium as in claim 100 wherein said estimates are used to decide how to perform said assigning.
Claim 111
Dependent Claim
25 words
A machine readable medium as in claim 102 wherein a user considers said estimates and selects a command to decide how to perform said assigning.
Claim 112
Dependent Claim
49 words
A machine readable medium as in claim 93 wherein said ICs each comprise a programmable logic device and wherein said method further comprises: testing a prototype of a system with said ICs; performing a synthesis of said HDL code to generate at least one Application Specific Integrated Circuit (ASIC).
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