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US6433402B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Selective copper alloy deposition

Assignee: Advanced Micro Devices Inc
•
Filing: 2000-11-16
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Granted: 2002-08-13
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Expires: 2020-11-16
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Abstract

Abstract Copper or a low resistivity copper alloy is initially deposited to fill relatively narrow openings leaving relatively wider openings unfilled. A copper alloy having improved electromigration resistance with respect to copper is then selectively deposited to fill the relatively wider openings, thereby improving electromigration resistance without increasing narrow line resistance. Embodiments include annealing after filling the relatively narrow openings and before filling the relatively wider openings, thereby reducing void formation in narrow lines.

Inventors

  • 👤 Christy Mei-Chu Woo
  • 👤 Pin-Chin Connie Wang
  • 👤 Amit Marathe
  • 👤 Diana M. Schonauer

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 06:51
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/032; H10W20/033; H10W20/037; H10W20/055; H10W20/056

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 143 words
A semiconductor device comprising: an interlayer dielectric (ILD); a plurality of trenches in the ILD, the plurality of trenches comprising: a plurality of small trenches having a width no greater than a first width; and a plurality of large trenches having width greater than the first width; and metal lines filling the trenches; wherein: the metal lines filling the small trenches comprise substantially pure copper (Cu) or a first Cu alloy; and the metal lines filling the large trenches comprise a lower layer of substantially pure Cu or the first Cu alloy and an upper layer of a second Cu alloy on the lower layer, the second Cu alloy containing an element in a sufficient amount such that the electromigration resistance of the second Cu alloy is greater than that of substantially pure Cu and greater than that of the first Cu alloy.
Claim 2
Dependent Claim 143 words
A semiconductor device comprising: an interlayer dielectric (ILD); a plurality of trenches in the ILD, the plurality of trenches comprising: a plurality of small trenches having a width no greater than a first width; and a plurality of large trenches having width greater than the first width; and metal lines filling the trenches; wherein: the metal lines filling the small trenches comprise substantially pure copper (Cu) or a first Cu alloy; and the metal lines filling the large trenches comprise a lower layer of substantially pure Cu or the first Cu alloy and an upper layer of a second Cu alloy on the lower layer, the second Cu alloy containing an element in a sufficient amount such that the electromigration resistance of the second Cu alloy is greater than that of substantially pure Cu and greater than that of the first Cu alloy.
Claim 3
Dependent Claim 30 words
The semiconductor device according to claim 1 , comprising vias including a via having a smallest via width, wherein the first width is about five times the smallest via width.
Claim 4
Dependent Claim 25 words
The semiconductor device according to claim 1 , comprising substantially pure Cu filling the small trenches and forming the lower layer in the large trenches.
Claim 5
Dependent Claim 29 words
The semiconductor device according to claim 1 , comprising an encapsulating layer on an upper surface of the second Cu alloy comprising an element of the second Cu alloy.
Claim 6
Dependent Claim 27 words
The semiconductor device according to claim 1 , comprising a barrier layer lining the trenches with the substantially pure Cu or Cu alloy on the barrier layer.
Claim 7
Dependent Claim 35 words
The semiconductor device according to claim 1 , wherein the small trenches filled with substantially pure Cu or the first Cu alloy have a width no greater than about 0.15 micron to about 7.5 microns.

References Cited (Backward Citations)

US5354712A Cited
US5731245A Cited
US6258710B1 Cited
US5972192A Cited
JPH11102909A Cited
US6022808A Cited
US6184137B1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2005-08-12 2006-02-11 2006-08-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2009-08-12 2010-02-11 2010-08-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2013-08-12 2014-02-11 2014-08-13 $7700.00 Window Closed / Lapsed

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