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US6022808A Expired / Lapsed US ⏱️ 0.0 years remaining

Copper interconnect methodology for enhanced electromigration resistance

Assignee: GlobalFoundries Inc
•
Filing: 1998-03-16
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Granted: 2000-02-08
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Expires: 2018-03-16
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Abstract

Abstract Copper interconnects with enhanced electromigration are formed by filling a via/contact hole and/or trench in a dielectric layer with undoped Cu. A Cu layer containing a dopant element, such as Pd, Zr or Sn is deposited on the undoped Cu contact/via and/or line. Annealing is then conducted to diffuse the dopant element into the copper contact/via and/or line to improve its electromigration resistance. CMP is then performed.

Inventors

  • 👤 Takeshi Nogami
  • 👤 Shekhar Pramanick
  • 👤 Dirk Brown

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 09:52
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/44; H10W20/4403; H10W20/4421; H10W20/4424; H10W20/01; H10W20/031; H10W20/056; H10W20/425

Claims Analysis

Total Claims: 22
Claim 1
Independent Claim 68 words
A method of manufacturing a semiconductor device, the method comprising: forming a contact/via hole and/or trench in a dielectric layer; depositing substantially undoped copper filling the hole and/or trench; depositing a layer of copper containing a dopant element on the undoped copper; and annealing to diffuse the dopant element into the copper filled contact/via hole and/or trench, thereby enhancing the electromigration resistance of the copper-filled hole or trench.
Claim 2
Independent Claim 68 words
A method of manufacturing a semiconductor device, the method comprising: forming a contact/via hole and/or trench in a dielectric layer; depositing substantially undoped copper filling the hole and/or trench; depositing a layer of copper containing a dopant element on the undoped copper; and annealing to diffuse the dopant element into the copper filled contact/via hole and/or trench, thereby enhancing the electromigration resistance of the copper-filled hole or trench.
Claim 3
Dependent Claim 33 words
The method of claim 1, further comprising planarizing by chemical mechanical polishing after annealing, so that the copper filled hole and/or trench is substantially coplanar with an upper surface of the dielectric layer.
Claim 4
Dependent Claim 20 words
The method according to claim 2, comprising depositing the undoped copper layer in a contact/via hole to form a contact/via.
Claim 5
Dependent Claim 19 words
The method according to claim 2, comprising depositing the undoped copper in a trench to form an interconnect line.
Claim 6
Dependent Claim 19 words
The method according to claim 1, comprising depositing the undoped copper by chemical vapor deposition, electroplating or electroless plating.
Claim 7
Dependent Claim 30 words
The method according to claim 1, comprising initially depositing a barrier layer on an upper surface of the surface of the dielectric layer and lining the contact/via hole and/or trench.
Claim 8
Dependent Claim 25 words
The method according to claim 6, comprising; depositing a seed layer on the barrier layer; and depositing the undoped copper by electroplating or electroless plating.
Claim 9
Dependent Claim 23 words
The method according to claim 1, comprising depositing the doped copper layer at a thickness of about 1,000 Å to about one micron.
Claim 10
Dependent Claim 23 words
The method according to claim 8, comprising depositing the doped copper layer at a thickness of about 3,000 Å to about 6,000 Å.
Claim 11
Dependent Claim 27 words
The method according to claim 1, comprising annealing at a temperature of about 300° C. to about 500° C. for about 10 minutes to about 2 hours.
Claim 12
Dependent Claim 25 words
The method according to claim 10, comprising annealing at a temperature of about 350° to about 450° for about 30 minutes to about 1 hour.
Claim 13
Dependent Claim 13 words
The method according to claim 1, comprising sputter depositing the doped copper layer.
Claim 14
Dependent Claim 23 words
The method according to claim 1, wherein the doped copper layer contains about 0.5 to about 12% by weight of the dopant element.
Claim 15
Dependent Claim 25 words
The method according to claim 13, wherein the doped cop per layer c ontains about 0.5 to about 6% by weight of the dopant element.
Claim 16
Dependent Claim 30 words
The method according to claim 1, comprising annealing is conducted so that the copper filled hole and/or trench contains about 3% to about 6% by weight of the dopant element.
Claim 17
Dependent Claim 28 words
The method according to claim 15, comprising annealing so that the copper filled hole and/or trench contains about 0.5 to about 2% by weight of the dopant element.
Claim 18
Dependent Claim 17 words
The method according to claim 1, wherein the dopant is palladium, zirconium, tin, magnesium, chromium or tantalum.
Claim 19
Dependent Claim 34 words
The method according to claim 17, wherein the dopant is tin and, after annealing, is present in the copper filled hole and/or trench in an amount of about 0.3 to about 1% by weight.
Claim 20
Independent Claim 163 words
A method of manufacturing a semiconductor device, the method comprising sequentially; forming a contact/via hole and/or trench in a dielectric layer; depositing a barrier layer on an upper surface of the dielectric layer lining the hole and/or trench; depositing substantially undoped copper by chemical vapor deposition, electroplating or electroless plating, filling the hole and/or trench; sputter depositing a layer of copper containing about 0.5 to about 12 weight percent of a dopant element at a thickness of about 1000 Å to about 1 micron on the undoped copper; annealing at a temperature of about 300° C. to about 500° C. for about thirty minutes to about two hours to diffuse the dopant element into the copper filled hole and/or trench, so that the copper filled hole and/or trench contains about 0.3% to about 6 weight percent of the dopant element; and chemical mechanical polishing so that the copper filled hole and/or trench is substantially coplanar with the upper surface of the dielectric layer.
Claim 21
Independent Claim 163 words
A method of manufacturing a semiconductor device, the method comprising sequentially; forming a contact/via hole and/or trench in a dielectric layer; depositing a barrier layer on an upper surface of the dielectric layer lining the hole and/or trench; depositing substantially undoped copper by chemical vapor deposition, electroplating or electroless plating, filling the hole and/or trench; sputter depositing a layer of copper containing about 0.5 to about 12 weight percent of a dopant element at a thickness of about 1000 Å to about 1 micron on the undoped copper; annealing at a temperature of about 300° C. to about 500° C. for about thirty minutes to about two hours to diffuse the dopant element into the copper filled hole and/or trench, so that the copper filled hole and/or trench contains about 0.3% to about 6 weight percent of the dopant element; and chemical mechanical polishing so that the copper filled hole and/or trench is substantially coplanar with the upper surface of the dielectric layer.
Claim 22
Dependent Claim 18 words
The method according to claim 19, wherein the dopant element comprises palladium, zirconium, tin, magnesium, chromium or tantalum.

References Cited (Backward Citations)

US4789648A Cited
US5447599A Cited
US5391517A Cited
US5674787A Cited
US5744376A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2003-02-07 2003-08-09 2004-02-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2007-02-07 2007-08-09 2008-02-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2011-02-07 2011-08-09 2012-02-08 $7700.00 Window Closed / Lapsed

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