Patent US5068887A successfully refreshed from Google Patents.
Patent US6429096B1 successfully refreshed from Google Patents.
US6429096B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making thinned, stackable semiconductor device
Assignee: Sony Corp
•
Filing: 2000-03-22
•
Granted: 2002-08-06
•
Expires: 2020-03-22
Abstract
Abstract A method of manufacturing a semiconductor device, comprising preparing a semiconductor device wafer which is formed with an LSI; working the semiconductor device wafer from the back surface thereof, thereby to diminish the thickness of the semiconductor device wafer to at most 200 [μm]; forming penetrant apertures in the resulting semiconductor device wafer; forming wiring plugs ( 23 in FIG. 7 ) in the respective penetrant apertures; dicing the semiconductor device wafer, thereby to be divided into semiconductor chips ( 7 ) each of which includes the wiring plugs ( 23 ); and mounting at least two of the semiconductor chips ( 7 ) over a printed-wiring circuit board ( 25 ) through bumps ( 10 ) connected with the wiring plugs ( 23 ). Thus, the ultrathin stacked multilevel mounting of semiconductor device components can be realized at a high reliability and with a high functionality.
Inventors
- 👤 Toshiharu Yanagida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-10 02:07
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/021; H10W20/023; H10W72/00; H10W72/071; H10W20/0238; H10W20/0265; H10W20/20; H10W90/00; H10W72/01; H10W72/012; H10W72/01251; H10W72/01255; H10W72/019; H10W72/20; H10W72/241; H10W72/244; H10W72/251; H10W72/50; H10W72/551; H10W72/552; H10W72/5522; H10W72/90; H10W72/921; H10W72/923; H10W72/941; H10W72/9415; H10W74/00; H10W90/20; H10W90/297; H10W90/701; H10W90/721; H10W90/722
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
164 words
A method of manufacturing a semiconductor device, comprising: presenting a semiconductor device wafer comprising a large-scale integrated circuit and an electrode pad lying at a peripheral edge of the large-scale integrated circuit on a circuit side, the semiconductor device wafer further comprising a back surface that includes a plurality of flaws that are a result of at least a process by which the large-scale integrated circuit is formed; working the semiconductor device wafer from the back surface to diminish a first thickness of the semiconductor device wafer to at least until the plurality of flaws are removed so as to form a thinned wafer; coating both a front surface and the back surface of the thinned wafer with a first insulating material to form a first coated wafer; forming a hole through each coating of insulating material, the electrode pad, and the thinned wafer; and forming in the hole a wiring plug to join the front and back surfaces of the first coated wafer.
Claim 2
Independent Claim
164 words
A method of manufacturing a semiconductor device, comprising: presenting a semiconductor device wafer comprising a large-scale integrated circuit and an electrode pad lying at a peripheral edge of the large-scale integrated circuit on a circuit side, the semiconductor device wafer further comprising a back surface that includes a plurality of flaws that are a result of at least a process by which the large-scale integrated circuit is formed; working the semiconductor device wafer from the back surface to diminish a first thickness of the semiconductor device wafer to at least until the plurality of flaws are removed so as to form a thinned wafer; coating both a front surface and the back surface of the thinned wafer with a first insulating material to form a first coated wafer; forming a hole through each coating of insulating material, the electrode pad, and the thinned wafer; and forming in the hole a wiring plug to join the front and back surfaces of the first coated wafer.
Claim 3
Dependent Claim
108 words
A method of manufacturing a semiconductor device as defined in claim 1 , wherein the first thickness of the semiconductor device wafer is reduced to a second thickness that substantially is not less than 100 μm and, after forming the hole, the method further comprising: coating the front and back surfaces of the first coated wafer with a second insulating material to fill up the hole with the second insulating material and to form a second coated wafer; and forming a penetrant aperture in the second insulating material contained in the hole, wherein the penetrant aperture defines a diameter that is smaller than a diameter of the hole.
Claim 4
Independent Claim
251 words
A method of manufacturing a semiconductor device, comprising in the following order: presenting a semiconductor device wafer comprising a large-scale integrated circuit and an electrode pad lying at a peripheral edge of the large-scale integrated circuit; working the semiconductor device wafer from a back surface to diminish a first thickness of the semiconductor device wafer to a second thickness that substantially is not less than 100 μm, wherein the resulting wafer defines a thinned wafer; coating both a front surface and the back surface of the thinned wafer with a first insulating material to form a first coated wafer; forming a hole through each coating of insulating material, the electrode pad, and the semiconductor device wafer; coating the front and back surfaces of the first coated wafer with a second insulating material to form a second coated wafer and to fill up the hole with the second insulating material; forming in the second insulating material contained in the hole a penetrant aperture having a diameter that is smaller than a diameter of the hole so as to leave insulating material from the second insulating material on an inwall of the hole; forming wiring layers which join an interior of the penetrant aperture and the front and back surfaces of the semiconductor device wafer; and patterning the wiring layers to form a wiring plug that includes respective electrode pads on a front and back surface of the second coated wafer to join the front and back surfaces of the second coated wafer.
Claim 5
Independent Claim
251 words
A method of manufacturing a semiconductor device, comprising in the following order: presenting a semiconductor device wafer comprising a large-scale integrated circuit and an electrode pad lying at a peripheral edge of the large-scale integrated circuit; working the semiconductor device wafer from a back surface to diminish a first thickness of the semiconductor device wafer to a second thickness that substantially is not less than 100 μm, wherein the resulting wafer defines a thinned wafer; coating both a front surface and the back surface of the thinned wafer with a first insulating material to form a first coated wafer; forming a hole through each coating of insulating material, the electrode pad, and the semiconductor device wafer; coating the front and back surfaces of the first coated wafer with a second insulating material to form a second coated wafer and to fill up the hole with the second insulating material; forming in the second insulating material contained in the hole a penetrant aperture having a diameter that is smaller than a diameter of the hole so as to leave insulating material from the second insulating material on an inwall of the hole; forming wiring layers which join an interior of the penetrant aperture and the front and back surfaces of the semiconductor device wafer; and patterning the wiring layers to form a wiring plug that includes respective electrode pads on a front and back surface of the second coated wafer to join the front and back surfaces of the second coated wafer.
Claim 6
Dependent Claim
35 words
A method of manufacturing a semiconductor device as defined in claim 3 , wherein the wiring plug is formed by subjecting the second coated wafer first to electroless plating and then to electroplating in succession.
Claim 7
Dependent Claim
63 words
A method of manufacturing a semiconductor device as defined in claim 4 , wherein the first and second insulating materials are made of a member selected from the group consisting of a liquefied resin and an organic resist material, and wherein the first thickness of the semiconductor device wafer is reduced to a second thickness that substantially is not less than 200 μm.
Claim 8
Independent Claim
119 words
A method of manufacturing a semiconductor device, comprising in the following order: presenting a semiconductor device wafer comprising a large-scale integrated circuit; working the semiconductor device wafer from a back surface to diminish a first thickness of the semiconductor device wafer to a second thickness that substantially is not less than 100 μm, wherein the resulting wafer defines a thinned wafer; forming penetrant apertures in the thinned wafer; forming wiring plugs in the respective penetrant apertures of the thinned wafer; dicing the thinned wafer into semiconductor chips, wherein each semiconductor chip includes wiring plugs; and stacking and mounting at least two of the semiconductor chips over a printed-wiring circuit board through means for connecting connected with the wiring plugs.
Claim 9
Independent Claim
119 words
A method of manufacturing a semiconductor device, comprising in the following order: presenting a semiconductor device wafer comprising a large-scale integrated circuit; working the semiconductor device wafer from a back surface to diminish a first thickness of the semiconductor device wafer to a second thickness that substantially is not less than 100 μm, wherein the resulting wafer defines a thinned wafer; forming penetrant apertures in the thinned wafer; forming wiring plugs in the respective penetrant apertures of the thinned wafer; dicing the thinned wafer into semiconductor chips, wherein each semiconductor chip includes wiring plugs; and stacking and mounting at least two of the semiconductor chips over a printed-wiring circuit board through means for connecting connected with the wiring plugs.
Claim 10
Dependent Claim
28 words
A method of manufacturing a semiconductor device as defined in claim 6 , wherein working the semiconductor device wafer includes one of grinding, chemical mechanical polishing, and etching.
Claim 11
Dependent Claim
68 words
A method of manufacturing a semiconductor device as defined in claim 6 , wherein the means for connecting includes at least one member selected from the group consisting of a solder ball bump, a wire bump, an anisotropic conductive film, and a conductive paste, and wherein the first thickness of the semiconductor device wafer is reduced to a second thickness that substantially is not less than 200 μm.
Claim 12
Independent Claim
189 words
A method to manufacture a semiconductor device, comprising in the following order: presenting a wafer defining a first thickness, wherein the wafer comprises a large-scale integrated (LSI) circuit surface having at least one electrode pad, the wafer further comprising a second surface, wherein the second surface includes a plurality of flaws that are a result of at least a process by which the large-scale integrated circuit surface is formed; grinding the second surface of the wafer at least until the plurality of flaws are removed to create a third surface; polishing the third surface of the wafer; forming a penetrant hole between the LSI circuit surface and the third surface and through the at least one electrode pad while restraining a tapering angle of the penetrant hole from widening at an open end; curing penetrant hole resin in the penetrant hole and over the at least one electrode pad; forming a via hole through the penetrant hole resin so as to leave a uniform layer of penetrant hole resin between the via hole and the penetrant hole; and packing a metal plug into the via hole without developing voids.
Claim 13
Independent Claim
189 words
A method to manufacture a semiconductor device, comprising in the following order: presenting a wafer defining a first thickness, wherein the wafer comprises a large-scale integrated (LSI) circuit surface having at least one electrode pad, the wafer further comprising a second surface, wherein the second surface includes a plurality of flaws that are a result of at least a process by which the large-scale integrated circuit surface is formed; grinding the second surface of the wafer at least until the plurality of flaws are removed to create a third surface; polishing the third surface of the wafer; forming a penetrant hole between the LSI circuit surface and the third surface and through the at least one electrode pad while restraining a tapering angle of the penetrant hole from widening at an open end; curing penetrant hole resin in the penetrant hole and over the at least one electrode pad; forming a via hole through the penetrant hole resin so as to leave a uniform layer of penetrant hole resin between the via hole and the penetrant hole; and packing a metal plug into the via hole without developing voids.
Claim 14
Dependent Claim
37 words
The method of claim 9 , wherein grinding the second surface of the wafer results in a wafer that defines a second thickness, wherein the second thickness substantially is not more than 30% of the first thickness.
Claim 15
Dependent Claim
20 words
The method of claim 10 , wherein the second thickness substantially is not more than 20% of the first thickness.
Claim 16
Dependent Claim
31 words
The method of claim 9 , wherein polishing the second surface of the wafer results in a wafer that defines a polished thickness that substantially is not less than 100 μm.
Claim 17
Dependent Claim
29 words
The method of claim 12 , wherein polishing the second surface of the wafer is by one of chemical mechanical polishing, wet acid etch polishing, and dry gas polishing.
Claim 18
Dependent Claim
50 words
The method of claim 9 , wherein restraining a tapering angle of the penetrant hole from widening at an open end includes curing resin on the LSI circuit surface and the third surface and forming the penetrant hole between the resin on the LSI circuit surface and the third surface.
Claim 19
Dependent Claim
21 words
The method of claim 9 , wherein the metal plug defines a funnel shape a first end and a second end.
Claim 20
Dependent Claim
23 words
The method of claim 9 , wherein packing the metal plug into the via hole includes employing electroless plating and then employing electroplating.
References Cited (Backward Citations)
US5646067A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-08-05 | 2006-02-04 | 2006-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-08-05 | 2010-02-04 | 2010-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-08-05 | 2014-02-04 | 2014-08-06 | $7700.00 | Window Closed / Lapsed |