Method of making thinned, stackable semiconductor device

Claim 1

A method of manufacturing a semiconductor device, comprising: presenting a semiconductor device wafer comprising a large-scale integrated circuit and an electrode pad lying at a peripheral edge of the large-scale integrated circuit on a circuit side, the semiconductor device wafer further comprising a back surface that includes a plurality of flaws that are a result of at least a process by which the large-scale integrated circuit is formed; working the semiconductor device wafer from the back surface to diminish a first thickness of the semiconductor device wafer to at least until the plurality of flaws are removed so as to form a thinned wafer; coating both a front surface and the back surface of the thinned wafer with a first insulating material to form a first coated wafer; forming a hole through each coating of insulating material, the electrode pad, and the thinned wafer; and forming in the hole a wiring plug to join the front and back surfaces of the first coated wafer.

Claim 2

A method of manufacturing a semiconductor device, comprising: presenting a semiconductor device wafer comprising a large-scale integrated circuit and an electrode pad lying at a peripheral edge of the large-scale integrated circuit on a circuit side, the semiconductor device wafer further comprising a back surface that includes a plurality of flaws that are a result of at least a process by which the large-scale integrated circuit is formed; working the semiconductor device wafer from the back surface to diminish a first thickness of the semiconductor device wafer to at least until the plurality of flaws are removed so as to form a thinned wafer; coating both a front surface and the back surface of the thinned wafer with a first insulating material to form a first coated wafer; forming a hole through each coating of insulating material, the electrode pad, and the thinned wafer; and forming in the hole a wiring plug to join the front and back surfaces of the first coated wafer.

Claim 4

A method of manufacturing a semiconductor device, comprising in the following order: presenting a semiconductor device wafer comprising a large-scale integrated circuit and an electrode pad lying at a peripheral edge of the large-scale integrated circuit; working the semiconductor device wafer from a back surface to diminish a first thickness of the semiconductor device wafer to a second thickness that substantially is not less than 100 μm, wherein the resulting wafer defines a thinned wafer; coating both a front surface and the back surface of the thinned wafer with a first insulating material to form a first coated wafer; forming a hole through each coating of insulating material, the electrode pad, and the semiconductor device wafer; coating the front and back surfaces of the first coated wafer with a second insulating material to form a second coated wafer and to fill up the hole with the second insulating material; forming in the second insulating material contained in the hole a penetrant aperture having a diameter that is smaller than a diameter of the hole so as to leave insulating material from the second insulating material on an inwall of the hole; forming wiring layers which join an interior of the penetrant aperture and the front and back surfaces of the semiconductor device wafer; and patterning the wiring layers to form a wiring plug that includes respective electrode pads on a front and back surface of the second coated wafer to join the front and back surfaces of the second coated wafer.

Claim 5

A method of manufacturing a semiconductor device, comprising in the following order: presenting a semiconductor device wafer comprising a large-scale integrated circuit and an electrode pad lying at a peripheral edge of the large-scale integrated circuit; working the semiconductor device wafer from a back surface to diminish a first thickness of the semiconductor device wafer to a second thickness that substantially is not less than 100 μm, wherein the resulting wafer defines a thinned wafer; coating both a front surface and the back surface of the thinned wafer with a first insulating material to form a first coated wafer; forming a hole through each coating of insulating material, the electrode pad, and the semiconductor device wafer; coating the front and back surfaces of the first coated wafer with a second insulating material to form a second coated wafer and to fill up the hole with the second insulating material; forming in the second insulating material contained in the hole a penetrant aperture having a diameter that is smaller than a diameter of the hole so as to leave insulating material from the second insulating material on an inwall of the hole; forming wiring layers which join an interior of the penetrant aperture and the front and back surfaces of the semiconductor device wafer; and patterning the wiring layers to form a wiring plug that includes respective electrode pads on a front and back surface of the second coated wafer to join the front and back surfaces of the second coated wafer.

Claim 8

A method of manufacturing a semiconductor device, comprising in the following order: presenting a semiconductor device wafer comprising a large-scale integrated circuit; working the semiconductor device wafer from a back surface to diminish a first thickness of the semiconductor device wafer to a second thickness that substantially is not less than 100 μm, wherein the resulting wafer defines a thinned wafer; forming penetrant apertures in the thinned wafer; forming wiring plugs in the respective penetrant apertures of the thinned wafer; dicing the thinned wafer into semiconductor chips, wherein each semiconductor chip includes wiring plugs; and stacking and mounting at least two of the semiconductor chips over a printed-wiring circuit board through means for connecting connected with the wiring plugs.

Claim 9

A method of manufacturing a semiconductor device, comprising in the following order: presenting a semiconductor device wafer comprising a large-scale integrated circuit; working the semiconductor device wafer from a back surface to diminish a first thickness of the semiconductor device wafer to a second thickness that substantially is not less than 100 μm, wherein the resulting wafer defines a thinned wafer; forming penetrant apertures in the thinned wafer; forming wiring plugs in the respective penetrant apertures of the thinned wafer; dicing the thinned wafer into semiconductor chips, wherein each semiconductor chip includes wiring plugs; and stacking and mounting at least two of the semiconductor chips over a printed-wiring circuit board through means for connecting connected with the wiring plugs.

Claim 12

A method to manufacture a semiconductor device, comprising in the following order: presenting a wafer defining a first thickness, wherein the wafer comprises a large-scale integrated (LSI) circuit surface having at least one electrode pad, the wafer further comprising a second surface, wherein the second surface includes a plurality of flaws that are a result of at least a process by which the large-scale integrated circuit surface is formed; grinding the second surface of the wafer at least until the plurality of flaws are removed to create a third surface; polishing the third surface of the wafer; forming a penetrant hole between the LSI circuit surface and the third surface and through the at least one electrode pad while restraining a tapering angle of the penetrant hole from widening at an open end; curing penetrant hole resin in the penetrant hole and over the at least one electrode pad; forming a via hole through the penetrant hole resin so as to leave a uniform layer of penetrant hole resin between the via hole and the penetrant hole; and packing a metal plug into the via hole without developing voids.

Claim 13

A method to manufacture a semiconductor device, comprising in the following order: presenting a wafer defining a first thickness, wherein the wafer comprises a large-scale integrated (LSI) circuit surface having at least one electrode pad, the wafer further comprising a second surface, wherein the second surface includes a plurality of flaws that are a result of at least a process by which the large-scale integrated circuit surface is formed; grinding the second surface of the wafer at least until the plurality of flaws are removed to create a third surface; polishing the third surface of the wafer; forming a penetrant hole between the LSI circuit surface and the third surface and through the at least one electrode pad while restraining a tapering angle of the penetrant hole from widening at an open end; curing penetrant hole resin in the penetrant hole and over the at least one electrode pad; forming a via hole through the penetrant hole resin so as to leave a uniform layer of penetrant hole resin between the via hole and the penetrant hole; and packing a metal plug into the via hole without developing voids.