Patent US6423619B1 successfully refreshed from Google Patents.
US6423619B1
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Transistor metal gate structure that minimizes non-planarity effects and method of formation
Assignee: NXP USA Inc
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Filing: 2001-11-30
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Granted: 2002-07-23
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Expires: 2021-11-30
Abstract
Abstract A metal gate structure is formed by depositing a gate dielectric, a gate electrode, a stop layer, and a metal layer within a gate trench and removing the portions of the layers that lie outside the gate trench. A first polish or etch process is used to remove a portion of the metal layer selective to the stop layer. A second polish or etch process is used to remove portions of the gate dielectric, the gate electrode, the stop layer and the metal layer which lie outside the gate trench after the first polish or etch process. The resulting structure increases the uniformity and non-planarity of the top surface of the metal gate structure.
Inventors
- 👤 John M. Grant
- 👤 Olubunmi O. Adetutu
- 👤 Yolanda S. Musgrove
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:40
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0225; H10P; H10P10/00; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01318; H10D64/60; H10D64/66; H10D64/667; H10D64/669
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
213 words
A transistor structure comprising: a substrate having first and second current electrodes formed therein and separated to define a channel area in the substrate; a control electrode stack overlying the channel area in the substrate, the control electrode stack having a lateral dimension determined by a sidewall spacer and having a height to define a control electrode trench, the control electrode stack further comprising: a control electrode dielectric directly adjoining the sidewall spacer and a region above the channel area, the control electrode dielectric filling a first portion of the control electrode trench; a control electrode layer directly adjoining the control electrode dielectric, the control electrode layer filling a second portion of the control electrode trench and having a material property that determines a threshold voltage value of the transistor structure; a conductive stop layer directly adjoining the control electrode layer, the conductive stop layer filling a third portion of the control electrode trench and providing a stop material that is used for selective layer removal of overlying materials during formation of the transistor structure; and a conductive layer directly adjoining the conductive stop layer, the conductive layer filling a fourth portion of the control electrode trench, the first portion, second portion, third portion and fourth portion substantially filling the control electrode trench.
Claim 2
Dependent Claim
213 words
A transistor structure comprising: a substrate having first and second current electrodes formed therein and separated to define a channel area in the substrate; a control electrode stack overlying the channel area in the substrate, the control electrode stack having a lateral dimension determined by a sidewall spacer and having a height to define a control electrode trench, the control electrode stack further comprising: a control electrode dielectric directly adjoining the sidewall spacer and a region above the channel area, the control electrode dielectric filling a first portion of the control electrode trench; a control electrode layer directly adjoining the control electrode dielectric, the control electrode layer filling a second portion of the control electrode trench and having a material property that determines a threshold voltage value of the transistor structure; a conductive stop layer directly adjoining the control electrode layer, the conductive stop layer filling a third portion of the control electrode trench and providing a stop material that is used for selective layer removal of overlying materials during formation of the transistor structure; and a conductive layer directly adjoining the conductive stop layer, the conductive layer filling a fourth portion of the control electrode trench, the first portion, second portion, third portion and fourth portion substantially filling the control electrode trench.
Claim 3
Dependent Claim
25 words
The transistor structure of claim 1 wherein the conductive stop layer is a polish stop layer for a chemical mechanical polish of the overlying materials.
Claim 4
Dependent Claim
25 words
The transistor structure of claim 1 wherein the conductive stop layer is a polish stop layer for a physical mechanical polish of the overlying materials.
Claim 5
Dependent Claim
24 words
The transistor structure of claim 1 wherein the conductive stop layer is an etch stop layer for chemical etch back of the overlying materials.
Claim 6
Dependent Claim
35 words
The transistor structure of claim 1 wherein the control electrode dielectric comprises one of a material selected from a group consisting of silicon dioxide, silicon-oxy-nitride, silicon nitride, metal silicates, metal aluminates, metal oxides and metal-oxy-nitrides.
Claim 7
Dependent Claim
31 words
The transistor structure of claim 1 wherein the control electrode layer comprises one a material selected from a group consisting of: metal nitrides, metal silicides, metal-silicon-nitrides, metal-aluminum-nitride and conductive metal oxides.
Claim 8
Dependent Claim
31 words
The transistor structure of claim 1 wherein the conductive stop layer comprises a conductive material that has a slower removal rate than the overlying materials during removal of the overlying materials.
Claim 9
Dependent Claim
19 words
The transistor structure of claim 7 wherein the conductive stop layer comprises a metal, a metal silicide or silicon.
Claim 10
Dependent Claim
13 words
The transistor structure of claim 1 wherein the conductive layer comprises a metal.
Claim 11
Dependent Claim
24 words
The transistor structure of claim 9 wherein the metal comprises a material selected from a group consisting of: tungsten, aluminum, gold, copper and silver.
Claim 12
Dependent Claim
41 words
The transistor structure of claim 1 further comprising: an interlevel dielectric adjoining an outer perimeter of the sidewall spacer, the interlevel dielectric electrically insulating the transistor structure and providing a second stop material for the selective layer removal of overlying materials.
Claim 13
Independent Claim
289 words
A method for providing a transistor, comprising: providing a substrate; forming first and second current electrodes in the substrate, the first and second current electrodes being separated to define a channel area in the substrate; forming a control electrode trench that determines location of a control electrode; and forming a control electrode stack within the control electrode trench, the forming of the control electrode stack further comprising: forming a control electrode dielectric within and beyond the control electrode trench and directly adjoining walls of the control electrode trench, the control electrode dielectric filling a first portion of the control electrode trench; forming a control electrode layer directly adjoining the control electrode dielectric, the control electrode layer filling a second portion of the control electrode trench and having a material property that determines a threshold voltage value of the transistor; forming a conductive stop layer directly adjoining the control electrode layer, the conductive stop layer filling a third portion of the control electrode trench and providing a stop material that is used for selective layer removal of overlying materials during formation of the transistor; forming a conductive layer directly adjoining the conductive stop layer, the conductive layer filling a fourth portion of the control electrode trench, the first portion, second portion, third portion and fourth portion substantially filling the control electrode trench opening; removing a first initial part of the conductive layer to form a first upper surface by using the conductive stop layer to stop the removing; and removing a second initial part of the conductive layer and part of the conductive stop layer, the control electrode layer and the control electrode dielectric to form a control electrode stack of the transistor that has a substantially planar upper surface.
Claim 14
Independent Claim
289 words
A method for providing a transistor, comprising: providing a substrate; forming first and second current electrodes in the substrate, the first and second current electrodes being separated to define a channel area in the substrate; forming a control electrode trench that determines location of a control electrode; and forming a control electrode stack within the control electrode trench, the forming of the control electrode stack further comprising: forming a control electrode dielectric within and beyond the control electrode trench and directly adjoining walls of the control electrode trench, the control electrode dielectric filling a first portion of the control electrode trench; forming a control electrode layer directly adjoining the control electrode dielectric, the control electrode layer filling a second portion of the control electrode trench and having a material property that determines a threshold voltage value of the transistor; forming a conductive stop layer directly adjoining the control electrode layer, the conductive stop layer filling a third portion of the control electrode trench and providing a stop material that is used for selective layer removal of overlying materials during formation of the transistor; forming a conductive layer directly adjoining the conductive stop layer, the conductive layer filling a fourth portion of the control electrode trench, the first portion, second portion, third portion and fourth portion substantially filling the control electrode trench opening; removing a first initial part of the conductive layer to form a first upper surface by using the conductive stop layer to stop the removing; and removing a second initial part of the conductive layer and part of the conductive stop layer, the control electrode layer and the control electrode dielectric to form a control electrode stack of the transistor that has a substantially planar upper surface.
Claim 15
Dependent Claim
63 words
The method of claim 12 further comprising: forming an interlevel dielectric adjoining an outer perimeter of the control electrode trench, the interlevel dielectric electrically insulating the transistor; and using the interlevel dielectric as a second stop material to remove the second initial part of the conductive layer and part of the conductive stop layer, the control electrode layer and the control electrode dielectric.
Claim 16
Dependent Claim
31 words
The method of claim 12 further comprising: forming the control electrode layer with a material selected from a group consisting of: metal nitrides, metal suicides, metal-silicon-nitrides, metal-aluminum-nitride and conductive metal oxides.
Claim 17
Dependent Claim
37 words
The method of claim 12 further comprising: forming the conductive stop layer with a conductive material that has a slower removal rate than the overlying materials during removal of the first initial part of the conductive layer.
Claim 18
Independent Claim
170 words
A method of forming within a gate trench a metal gate structure that minimizes non-planarity effects comprising: forming a gate dielectric adjoining all surfaces of the gate trench and extending beyond the gate trench; forming a gate electrode layer of a first metal adjoining the gate dielectric and extending beyond the gate trench, the gate electrode layer filling less than all of the gate trench; forming a stop layer adjoining all exposed surfaces of the gate electrode layer and extending beyond the gate trench, the stop layer also filling less than all of the gate trench; forming a conductive layer of a second metal adjoining all exposed surfaces of the stop layer and extending beyond the gate trench, the conductive layer substantially filling the gate trench; removing all portions of the conductive layer above the stop layer by using the stop layer to substantially retard the removing; and removing all portions of the conductive layer, the stop layer, the gate electrode layer and the gate dielectric above a predetermined height.
Claim 19
Independent Claim
170 words
A method of forming within a gate trench a metal gate structure that minimizes non-planarity effects comprising: forming a gate dielectric adjoining all surfaces of the gate trench and extending beyond the gate trench; forming a gate electrode layer of a first metal adjoining the gate dielectric and extending beyond the gate trench, the gate electrode layer filling less than all of the gate trench; forming a stop layer adjoining all exposed surfaces of the gate electrode layer and extending beyond the gate trench, the stop layer also filling less than all of the gate trench; forming a conductive layer of a second metal adjoining all exposed surfaces of the stop layer and extending beyond the gate trench, the conductive layer substantially filling the gate trench; removing all portions of the conductive layer above the stop layer by using the stop layer to substantially retard the removing; and removing all portions of the conductive layer, the stop layer, the gate electrode layer and the gate dielectric above a predetermined height.
Claim 20
Dependent Claim
50 words
The method of claim 16 further comprising: removing any of the conductive layer of the second metal, the stop layer, the gate electrode layer and the gate dielectric by one of the following removal techniques consisting of chemical mechanical polishing (CMP), mechanical polishing, chemical polishing, etch-back processing, or sputter removal.
Claim 21
Dependent Claim
68 words
The method of claim 16 wherein each of forming the gate dielectric, the gate electrode layer, forming the stop layer and forming the conductive layer further comprises forming each of the gate dielectric, the gate electrode layer, the stop layer and the conductive layer by depositing by any of either physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE) or plating.
Claim 22
Dependent Claim
53 words
The method of claim 16 wherein the step of forming the gate electrode layer further comprises forming the gate electrode layer from a material selected from a group consisting of titanium nitride, tantalum nitride, titanium silicon nitride, tantalum silicon nitride, iridium oxide, ruthenium oxide, tungsten nitride, tungsten silicon nitride and titanium aluminum nitride.
Claim 23
Dependent Claim
34 words
The method of claim 16 wherein the step of forming the stop layer further comprises forming the stop layer from a material selected from a group consisting of titanium, tantalum, silicon, gold and silver.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-07-22 | 2006-01-21 | 2006-07-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-07-22 | 2010-01-21 | 2010-07-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-07-22 | 2014-01-21 | 2014-07-23 | $7700.00 | Window Closed / Lapsed |