Patent US6411145B1 successfully refreshed from Google Patents.
US6411145B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Feedback control of clock duty cycle
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 2001-06-14
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Granted: 2002-06-25
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Expires: 2021-06-14
Abstract
Abstract A circuit configured to correct a duty cycle error or vary the duty cycle of a clock signal. The circuit includes a differential amplifier or control circuit that receives differential signal inputs. At least one differential pair of transistors is connected to outputs of the differential amplifier or control circuit. Outputs of the one or more differential pairs of transistors are connected to inputs of a differential circuit. The differential amplifier or control circuit is connected to the outputs of the differential circuit. The one or more differential pairs of transistors is configured to change a DC level of at least one of the inputs of the differential circuit in order to shift a cross over point of the inputs of the differential circuit and thereby effect a duty cycle change (or correction) at the outputs of the differential circuit.
Inventors
- 👤 Jeff S. Kueng
- 👤 Justin J. Kraus
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 09:33
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/156; H03K5/1565
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
107 words
A circuit configured to correct a duty cycle error of a clock signal, said circuit comprising: a pair of inputs configured to receive differential signals, wherein a difference between said differential signals generally indicates the duty cycle error of the clock signal; a differential amplifier connected to said inputs, said differential amplifier having outputs; a differential pair of transistors connected to said outputs of said differential amplifier, said differential pair of transistors configured to shift a cross over point of the signals carried at the outputs of said differential amplifier, further comprising a plurality of differential pairs of transistors connected to said outputs of said differential amplifier.
Claim 2
Dependent Claim
107 words
A circuit configured to correct a duty cycle error of a clock signal, said circuit comprising: a pair of inputs configured to receive differential signals, wherein a difference between said differential signals generally indicates the duty cycle error of the clock signal; a differential amplifier connected to said inputs, said differential amplifier having outputs; a differential pair of transistors connected to said outputs of said differential amplifier, said differential pair of transistors configured to shift a cross over point of the signals carried at the outputs of said differential amplifier, further comprising a plurality of differential pairs of transistors connected to said outputs of said differential amplifier.
Claim 3
Dependent Claim
21 words
A circuit its recited in claim 1 , wherein said differential signals received at the pair of inputs comprises DC signals.
Claim 4
Dependent Claim
130 words
A circuit configured to correct a duty cycle error of a clock signal, said circuit comprising: a pair of inputs configured to receive differential signals, wherein a difference between said differential signals generally indicates the duty cycle error of the clock signal; a differential amplifier connected to said inputs, said differential amplifier having outputs; a differential pair of transistors connected to said outputs of said differential amplifier, said differential pair of transistors configured to shift a cross over point of the signals carried at the outputs of said differential amplifier, wherein said circuit includes a differential circuit having inputs and outputs, wherein outputs of said differential pair of transistors are connected to inputs of said differential circuit, and said differential amplifier is connected to the outputs of said differential circuit.
Claim 5
Dependent Claim
130 words
A circuit configured to correct a duty cycle error of a clock signal, said circuit comprising: a pair of inputs configured to receive differential signals, wherein a difference between said differential signals generally indicates the duty cycle error of the clock signal; a differential amplifier connected to said inputs, said differential amplifier having outputs; a differential pair of transistors connected to said outputs of said differential amplifier, said differential pair of transistors configured to shift a cross over point of the signals carried at the outputs of said differential amplifier, wherein said circuit includes a differential circuit having inputs and outputs, wherein outputs of said differential pair of transistors are connected to inputs of said differential circuit, and said differential amplifier is connected to the outputs of said differential circuit.
Claim 6
Dependent Claim
58 words
A circuit as recited in claim 3 , wherein said differential pair of transistors is configured to pull at least one of the inputs of said differential circuit down in order to shift a cross over point of the inputs of the differential circuit and thereby effect a duty cycle change at the outputs of the differential circuit.
Claim 7
Dependent Claim
21 words
A circuit as recited in claim 4 , wherein said differential signals received at the pair of inputs comprises DC signals.
Claim 8
Dependent Claim
21 words
A circuit as recited in claim 3 , wherein said differential signals received at the pair of inputs comprises DC signals.
Claim 9
Dependent Claim
147 words
A circuit configured to correct a duty cycle error of a clock signal, said circuit comprising: a pair of inputs configured to receive differential signals, wherein a difference between said differential signals generally indicates the duty cycle error of the clock signal; a differential amplifier connected to said inputs, said differential amplifier having outputs; a differential pair of transistors connected to said outputs of said differential amplifier, said differential pair of transistors configured to shift a cross over point of the signals carried at the outputs of said differential amplifier, further comprising a plurality of differential pairs of transistors connected to said outputs of said differential amplifier, wherein said circuit includes a differential circuit having inputs and outputs, wherein outputs of said differential pair of transistors are connected to inputs of said differential circuit, and said differential amplifier is connected to the outputs of said differential circuit.
Claim 10
Dependent Claim
147 words
A circuit configured to correct a duty cycle error of a clock signal, said circuit comprising: a pair of inputs configured to receive differential signals, wherein a difference between said differential signals generally indicates the duty cycle error of the clock signal; a differential amplifier connected to said inputs, said differential amplifier having outputs; a differential pair of transistors connected to said outputs of said differential amplifier, said differential pair of transistors configured to shift a cross over point of the signals carried at the outputs of said differential amplifier, further comprising a plurality of differential pairs of transistors connected to said outputs of said differential amplifier, wherein said circuit includes a differential circuit having inputs and outputs, wherein outputs of said differential pair of transistors are connected to inputs of said differential circuit, and said differential amplifier is connected to the outputs of said differential circuit.
Claim 11
Dependent Claim
21 words
A circuit as recited in claim 7 , wherein said differential signals received at the pair of inputs comprises DC signals.
Claim 12
Dependent Claim
61 words
A circuit as recited in claim 7 , wherein said differential pairs of transistors are configured to change a DC level of at least one of the inputs of said differential circuit in order to shift a cross over point of the inputs of the differential circuit and thereby effect a duty cycle change at the outputs of the differential circuit.
Claim 13
Dependent Claim
21 words
A circuit as recited in claim 9 , wherein said differential signals received at the pair of inputs comprises DC signals.
Claim 14
Dependent Claim
168 words
A circuit configured to correct a duty cycle error of a clock signal, said circuit comprising: a pair of inputs configured to receive differential signals, wherein a difference between said differential signals generally indicates the duty cycle error of the clock signal; a differential amplifier connected to said inputs, said differential amplifier having outputs; at least one differential pair of transistors connected to said outputs of said differential amplifier, wherein said circuit includes a differential circuit having inputs and outputs, wherein outputs of said at least one differential pair of transistors are connected to inputs of said differential circuit, and said differential amplifier is connected to the outputs of said differential circuit, wherein said at least one differential pair of transistors is configured to change a DC level of at least one of the inputs of said differential circuit in order to shift a cross over point of the inputs of the differential circuit and thereby effect a duty cycle change at the outputs of the differential circuit.
Claim 15
Dependent Claim
168 words
A circuit configured to correct a duty cycle error of a clock signal, said circuit comprising: a pair of inputs configured to receive differential signals, wherein a difference between said differential signals generally indicates the duty cycle error of the clock signal; a differential amplifier connected to said inputs, said differential amplifier having outputs; at least one differential pair of transistors connected to said outputs of said differential amplifier, wherein said circuit includes a differential circuit having inputs and outputs, wherein outputs of said at least one differential pair of transistors are connected to inputs of said differential circuit, and said differential amplifier is connected to the outputs of said differential circuit, wherein said at least one differential pair of transistors is configured to change a DC level of at least one of the inputs of said differential circuit in order to shift a cross over point of the inputs of the differential circuit and thereby effect a duty cycle change at the outputs of the differential circuit.
Claim 16
Dependent Claim
89 words
A circuit configured to vary a duty cycle of a clock signal, said circuit comprising: a pair of inputs configured to receive differential signals; a control circuit connected to said inputs, said control circuit having outputs; a differential pair of transistors connected to said outputs of said control circuit, said differential pair of transistors configured to shift a cross over point of the signals carried at the outputs of said control circuit, further comprising a plurality of differential pairs of transistors connected to said outputs of said control circuit.
Claim 17
Dependent Claim
89 words
A circuit configured to vary a duty cycle of a clock signal, said circuit comprising: a pair of inputs configured to receive differential signals; a control circuit connected to said inputs, said control circuit having outputs; a differential pair of transistors connected to said outputs of said control circuit, said differential pair of transistors configured to shift a cross over point of the signals carried at the outputs of said control circuit, further comprising a plurality of differential pairs of transistors connected to said outputs of said control circuit.
Claim 18
Dependent Claim
21 words
A circuit as recited in claim 12 , wherein said differential signals received at the pair of inputs comprises DC signals.
Claim 19
Dependent Claim
112 words
A circuit configured to vary a duty cycle of a clock signal, said circuit comprising: a pair of inputs configured to receive differential signals; a control circuit connected to said inputs, said control circuit having outputs; a differential pair of transistors connected to said outputs of said control circuit, said differential pair of transistors configured to shift a cross over point of the signals carried at the outputs of said control circuit, wherein said circuit includes a differential circuit having inputs and outputs, wherein outputs of said differential pair of transistors are connected to inputs of said differential circuit, and said control circuit is connected to the outputs of said differential circuit.
Claim 20
Dependent Claim
112 words
A circuit configured to vary a duty cycle of a clock signal, said circuit comprising: a pair of inputs configured to receive differential signals; a control circuit connected to said inputs, said control circuit having outputs; a differential pair of transistors connected to said outputs of said control circuit, said differential pair of transistors configured to shift a cross over point of the signals carried at the outputs of said control circuit, wherein said circuit includes a differential circuit having inputs and outputs, wherein outputs of said differential pair of transistors are connected to inputs of said differential circuit, and said control circuit is connected to the outputs of said differential circuit.
Claim 21
Dependent Claim
21 words
A circuit as recited in claim 14 , wherein said differential signals received at the pair of inputs comprises DC signals.
Claim 22
Dependent Claim
61 words
A circuit as recited in claim 14 , wherein said differential pair of transistors is configured to change a DC level of at least one of the inputs of said differential circuit in order to shift a cross over point of the inputs of the differential circuit and thereby effect a duty cycle change at the outputs of the differential circuit.
Claim 23
Dependent Claim
21 words
A circuit as recited in claim 16 , wherein said differential signals received at the pair of inputs comprises DC signals.
Claim 24
Dependent Claim
129 words
A circuit configured to vary a duty cycle of a clock signal, said circuit comprising: a pair of inputs configured to receive differential signals; a control circuit connected to said inputs, said control circuit having outputs; a differential pair of transistors connected to said outputs of said control circuit, said differential pair of transistors configured to shift a cross over point of the signals carried at the outputs of said control circuit, further comprising a plurality of differential pairs of transistors connected to said outputs of said control circuit, wherein said circuit includes a differential circuit having inputs and outputs, wherein outputs of said differential pair of transistors are connected to inputs of said differential circuit, and said control circuit is connected to the outputs of said differential circuit.
Claim 25
Dependent Claim
129 words
A circuit configured to vary a duty cycle of a clock signal, said circuit comprising: a pair of inputs configured to receive differential signals; a control circuit connected to said inputs, said control circuit having outputs; a differential pair of transistors connected to said outputs of said control circuit, said differential pair of transistors configured to shift a cross over point of the signals carried at the outputs of said control circuit, further comprising a plurality of differential pairs of transistors connected to said outputs of said control circuit, wherein said circuit includes a differential circuit having inputs and outputs, wherein outputs of said differential pair of transistors are connected to inputs of said differential circuit, and said control circuit is connected to the outputs of said differential circuit.
Claim 26
Dependent Claim
61 words
A circuit as recited in claim 18 , wherein said differential pairs of transistors are configured to change a DC level of at least one of the inputs of said differential circuit in order to shift a cross over point of the inputs of the differential circuit and thereby effect a duty cycle change at the outputs of the differential circuit.
Claim 27
Dependent Claim
21 words
A circuit as recited in claim 19 , wherein said differential signals received at the pair of inputs comprises DC signals.
Claim 28
Dependent Claim
21 words
A circuit as recited in claim 18 , wherein said differential signals received at the pair of inputs comprises DC signals.
Claim 29
Dependent Claim
151 words
A circuit configured to vary a duty cycle error of a clock signal, said circuit comprising: a pair of inputs configured to receive differential signals; a control circuit connected to said inputs, said control circuit having outputs; at least one differential pair of transistors connected to said outputs of said control circuit, wherein said circuit includes a differential circuit having inputs and outputs, wherein outputs of said at least one differential pair of transistors are connected to inputs of said differential circuit, and said control circuit is connected to the outputs of said differential circuit, wherein said at least one differential pair of transistors is configured to change a DC level of at least one of the inputs of said differential circuit in order to shift a cross over point of the inputs of the differential circuit and thereby effect a duty cycle change at the outputs of the differential circuit.
Claim 30
Dependent Claim
151 words
A circuit configured to vary a duty cycle error of a clock signal, said circuit comprising: a pair of inputs configured to receive differential signals; a control circuit connected to said inputs, said control circuit having outputs; at least one differential pair of transistors connected to said outputs of said control circuit, wherein said circuit includes a differential circuit having inputs and outputs, wherein outputs of said at least one differential pair of transistors are connected to inputs of said differential circuit, and said control circuit is connected to the outputs of said differential circuit, wherein said at least one differential pair of transistors is configured to change a DC level of at least one of the inputs of said differential circuit in order to shift a cross over point of the inputs of the differential circuit and thereby effect a duty cycle change at the outputs of the differential circuit.
Claim 31
Independent Claim
111 words
A method of correcting a duty cycle error of a clock signal, said method comprising using a circuit to correct the duty cycle by providing differential signals to a pair of inputs of the circuit, wherein a difference between said differential signals generally indicates the duty cycle error of the clock signal, wherein the circuit includes a differential amplifier connected to the inputs, the differential amplifier has outputs, and a plurality of differential pair of transistors connected to the outputs of the differential amplifier, said method further comprising using the differential pairs of transistors to shift a cross over point of the signals carried at the outputs of the differential amplifier.
Claim 32
Independent Claim
111 words
A method of correcting a duty cycle error of a clock signal, said method comprising using a circuit to correct the duty cycle by providing differential signals to a pair of inputs of the circuit, wherein a difference between said differential signals generally indicates the duty cycle error of the clock signal, wherein the circuit includes a differential amplifier connected to the inputs, the differential amplifier has outputs, and a plurality of differential pair of transistors connected to the outputs of the differential amplifier, said method further comprising using the differential pairs of transistors to shift a cross over point of the signals carried at the outputs of the differential amplifier.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2005-06-24 | 2005-12-24 | 2006-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-06-24 | 2009-12-24 | 2010-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-06-24 | 2013-12-24 | 2014-06-25 | $7700.00 | Window Closed / Lapsed |