US5448196A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase shift circuit
Assignee: Toshiba Corp
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Filing: 1994-04-21
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Granted: 1995-09-05
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Expires: 2014-04-21
Abstract
Abstract A phase shift circuit suitable for use in an FM detecting circuit of quadrature detection method adopted for a FM radio receiver, for example. The phase shift circuit includes first and second pairs of differential transistors to which input signals are applied as differential inputs in common, first and second current sources for driving the first and second pairs of differential transistors, respectively, a first load circuit connected to respective collectors of the first pair of differential transistors, a second load circuit connected to an output side collector of the second pair of differential transistors and a third pair of differential transistors to which a first signal and a second signal are applied as differential inputs, wherein the first signal is derived from one of the collectors of the first pair of differential transistors, whereas the second signal is derived from the output side collector of the second pair of differential transistors. The resistance load circuit may be of Y-connection and Δ-connection. The resonant circuit is composed of a resistor and a ceramic resonator connected in parallel to each other. Since three differential transistor circuits are connected in parallel, it is possible to realize a low-voltage phase shift circuit which can be activated by a single battery (about 0.9 V).
Inventors
- 👤 Yoshihiko Kanbara
- 👤 Tsutomu Nakai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 07:23
CPC Classifications
H; H03; H03H; H03H11/00; H03H11/02; H03H11/16
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
199 words
A phase shift circuit, comprising: first and second pairs of differential transistors to which input signals are applied as differential inputs in common; first and second current sources for driving said first and second pairs of differential transistors, respectively; a first load circuit connected to respective collectors of said first pair of differential transistors; a second load circuit connected to an output side collector of said second pair of differential transistors; a third pair of differential transistors to which a first signal and a second signal are applied as differential inputs; and a third load circuit connected to respective collectors of said third pair of differential transistors, wherein said first signal is in-phase with one of the input signals and is derived from one of the collectors of said first pair of differential transistors, said second signal is out of phase with said one of the input signals and is derived from said output side collector of said second pair of differential transistors, and the third pair of differential transistors outputs a shifted signal at either collector to which the third load circuit is connected, the shifted signal being out of phase with said one of the input signals.
Claim 2
Dependent Claim
199 words
A phase shift circuit, comprising: first and second pairs of differential transistors to which input signals are applied as differential inputs in common; first and second current sources for driving said first and second pairs of differential transistors, respectively; a first load circuit connected to respective collectors of said first pair of differential transistors; a second load circuit connected to an output side collector of said second pair of differential transistors; a third pair of differential transistors to which a first signal and a second signal are applied as differential inputs; and a third load circuit connected to respective collectors of said third pair of differential transistors, wherein said first signal is in-phase with one of the input signals and is derived from one of the collectors of said first pair of differential transistors, said second signal is out of phase with said one of the input signals and is derived from said output side collector of said second pair of differential transistors, and the third pair of differential transistors outputs a shifted signal at either collector to which the third load circuit is connected, the shifted signal being out of phase with said one of the input signals.
Claim 3
Dependent Claim
20 words
The phase shift circuit of claim 1, wherein said first load circuit includes a plurality of resistors connected in Y-connection.
Claim 4
Dependent Claim
20 words
The phase shift circuit of claim 1, wherein said first load circuit includes a plurality of resistors connected in Δ-connection.
Claim 5
Dependent Claim
27 words
The phase shift circuit of claim 1, wherein said second load circuit includes a resonant circuit comprising a resistor and a ceramic resonator connected to each other.
Claim 6
Dependent Claim
59 words
The phase shift circuit of claim 1, wherein said second load circuit includes a resonant circuit comprising a resistor and a reactance element connected in parallel, the reactance element being having a resistance equal to that of the resistor at a predetermined frequency and the resistance of the reactance element being variable according to deviation from the predetermined frequency.
Claim 7
Dependent Claim
76 words
The phase shift circuit of any of claims 2 or 3, wherein a resistance of said first load circuit and a current value of said first current source are both adjusted so that dc potentials at differential inputs of said third pair of differential transistors become equal to each other and further real parts of the two in-phase signals outputted from collectors of the first and second pairs of differential transistors become equal to each other.
Claim 8
Dependent Claim
40 words
The phase shift circuit of claim 6, wherein an absolute impedance value at an intermediate frequency between a resonant point and an anti-resonant point of the ceramic resonator is equal to a resistance of the resistor of said resonant circuit.
Claim 9
Dependent Claim
58 words
The phase shift circuit of any of claims 4 or 5, wherein bases of said first pair of differential transistors are connected to bases of said second pair of differential transistors, respectively, so that the first signal and the second signal which is derived from said output side collector connected to said second load circuit have different phases.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-04 | 1999-03-06 | 1999-09-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-04 | 2003-03-06 | 2003-09-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-04 | 2007-03-06 | 2007-09-05 | $7700.00 | Window Closed / Lapsed |