US4922127A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase shift arrangement
Assignee: Plessey Semiconductors Ltd
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Filing: 1988-09-16
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Granted: 1990-05-01
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Expires: 2008-09-16
Abstract
Abstract A phase shift arrangement comprising bi-stable devices arranged to provide phase shifted output signals triggered by a clock pulse level. The bi-stable devices including biasing means such that the clock pulse level at which the bi-stable devices are triggered is adjusted. The adjustment of the triggering level providing an offset for the degree of phase shift between output signals.
Inventors
- 👤 Paul A. Denny
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 08:21
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/135; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; H03K3/2885; H03K5/15
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
180 words
A phase shift arrangement arranged to be coupled to a clock pulse source, said clock pulse source being arranged to provide clock pulse signals, the phase shift arrangement including bi-stable means, said bi-stable means comprising a first bi-stable device and a second bi-stable device, said bi-stable means being coupled to said clock pulse source to allow said first bi-stable device and said second bi-stable device to be triggered by a predetermined level of said clock pulse signal from said clock pulse source, said triggered first bi-stable device being arranged to provide first output signals, said triggered second bi-stable device being arranged to provide second output signals, said first output signals, having a specified phase relation with said second output signals, said first bi-stable device and said second bi-stable device respectively each including bias means, said bias means being arranged to adjust the said predetermined level of clock pulse signal at which said first bi-stable device and said second bi-stable device are triggered such that said specified phase relation between said first output signals and said second output signals is determinable.
Claim 2
Dependent Claim
180 words
A phase shift arrangement arranged to be coupled to a clock pulse source, said clock pulse source being arranged to provide clock pulse signals, the phase shift arrangement including bi-stable means, said bi-stable means comprising a first bi-stable device and a second bi-stable device, said bi-stable means being coupled to said clock pulse source to allow said first bi-stable device and said second bi-stable device to be triggered by a predetermined level of said clock pulse signal from said clock pulse source, said triggered first bi-stable device being arranged to provide first output signals, said triggered second bi-stable device being arranged to provide second output signals, said first output signals, having a specified phase relation with said second output signals, said first bi-stable device and said second bi-stable device respectively each including bias means, said bias means being arranged to adjust the said predetermined level of clock pulse signal at which said first bi-stable device and said second bi-stable device are triggered such that said specified phase relation between said first output signals and said second output signals is determinable.
Claim 3
Dependent Claim
22 words
A phase shift arrangement as claimed in claim 1 wherein the bi-stable devices are D-type flip-flop elements arranged in a master-slave configuration.
Claim 4
Dependent Claim
19 words
A phase shift arrangement as claimed in claim 1 wherein the specified phase relation is a quadrature phase relation.
Claim 5
Dependent Claim
134 words
A phase shift arrangement as claimed in claim 1 wherein said first bi-stable device and said second bi-stable device each including a first pair of transistor switches and a second pair of transistor switches, each transistor switch of said first pair of transistor switches and said second pair of transistor switches having an emitter, said emitters of said first pair of transistor switches being coupled to a first input transistor switch through its collector, said emitters of said second pair of transistor switches being coupled to a second input transistor switch through its collector, said first input transistor switch and said second input transistor switch being coupled by said bias means, and said bias means comprising means to provide a voltage bias between said first input transistor switch and said second input transistor switch.
Claim 6
Dependent Claim
28 words
A phase shift arrangement as claimed in claim 4 wherein the means for providing the voltage bias comprises externally accessable nodes whereto a voltage differential may be applied.
Claim 7
Dependent Claim
17 words
A phase shift arrangement as claimed in claim 4 wherein the bi-stable device input switches are transistors.
Claim 8
Dependent Claim
113 words
A phase shift arrangement as claimed in claim 4 wherein said voltage bias comprises a bias transistor pair coupled in parallel between said first input transistor switch and said second input transistor switch through their respective base, said bias transistor pair comprising a first bias transistor fabricated to have a first emitter area and a second bias transistor fabricated to have a second emitter area, said first emitter area and said second emitter area being respectively different in order to provide a voltage bias between said first input transistor switch and said second input transistor switch by ensuring a voltage differential between said first input transistor base and said second input transistor base.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-30 | 1993-10-30 | 1994-05-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-30 | 1997-10-30 | 1998-05-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-30 | 2001-10-30 | 2002-05-01 | $7700.00 | Window Closed / Lapsed |