Semiconductor integrated circuit

Claim 2

A semiconductor integrated circuit formed on a semiconductor substrate, comprising: a plurality of semiconductor element groups provided on a surface of said semiconductor substrate, each performing a prescribed operation; a first interconnection pattern provided above said plurality of semiconductor element groups, used as a local line for connecting semiconductor elements in each of said semiconductor element groups; a second interconnection pattern provided above said first interconnection pattern; and a third interconnection pattern provided above said second interconnection pattern, wherein said second interconnection pattern is used as a lower layer power supply line for applying a power supply potential to each of said semiconductor element groups, and said third interconnection pattern forms a plurality of upper layer signal lines for signal transmission between each of said semiconductor element groups and outside.

Claim 3

The semiconductor integrated circuit according to claim 1 , wherein said lower layer power supply line is provided to cover said local line.

Claim 4

The semiconductor integrated circuit according to claim 2 , wherein said second interconnection pattern is further used as a contact electrode for connecting said plurality of upper layer signal lines with each of said semiconductor element groups.

Claim 5

The semiconductor integrated circuit according to claim 1 , wherein said second and third interconnection patterns are used as lower layer and upper layer signal lines, respectively, for signal input/output between each of said semiconductor element groups and a portion in the substrate other than the semiconductor element group.

Claim 6

The semiconductor integrated circuit according to claim 4 , wherein said plurality of upper layer signal lines and said plurality of lower layer signal lines are provided at least partially not overlapping with each other.

Claim 7

The semiconductor integrated circuit according to claim 1 , wherein said third interconnection pattern further forms a upper layer power supply line for applying a power supply potential to each of said semiconductor element groups.

Claim 8

A semiconductor integrated circuit formed on a semiconductor substrate, comprising: a logic circuit including a plurality of transistor elements provided on a prescribed area of a surface of said semiconductor substrate, and a local line for coupling between said plurality of transistor elements, said local line formed by a first interconnection pattern provided above said plurality of transistor elements; a power supply line for supplying power supply potential to said logic circuit, said power supply line formed by a second interconnection pattern, said power supply line and prescribed area overlapping; a signal line for transmitting a signal between said logic circuit and other circuit, said signal line formed by a third interconnection pattern provided above said second interconnection pattern, said signal supply line and said prescribed area overlapping; a memory array region including a plurality of memory cells arranged in rows and columns on a surface of said semiconductor substrate, and a plurality of bit line pairs corresponding to said columns of the memory cells respectively, said first interconnection pattern being used as said bit line pairs, and thinner than said second interconnection pattern such that the capacitance of said bit line pairs are reduced, a resistivity of a material forming said first. interconnection pattern being smaller than the resistivity of tungsten silicide, said second interconnection pattern being thinner than said third interconnection pattern, and said signal line and said power supply line extending in the same direction wherein the signal line extends above the power supply line with no intervening conductive line therebetween.

Claim 9

A semiconductor integrated circuit formed on a semiconductor substrate, comprising: a logic circuit including a plurality of transistor elements provided on a prescribed area of a surface of said semiconductor substrate, and a local line for coupling between said plurality of transistor elements, said local line formed by a first interconnection pattern provided above said plurality of transistor elements; a power supply line for supplying power supply potential to said logic circuit, said power supply line formed by a second interconnection pattern, said power supply line and prescribed area overlapping; a signal line for transmitting a signal between said logic circuit and other circuit, said signal line formed by a third interconnection pattern provided above said second interconnection pattern, said signal supply line and said prescribed area overlapping; a memory array region including a plurality of memory cells arranged in rows and columns on a surface of said semiconductor substrate, and a plurality of bit line pairs corresponding to said columns of the memory cells respectively, said first interconnection pattern being used as said bit line pairs, and thinner than said second interconnection pattern such that the capacitance of said bit line pairs are reduced, a resistivity of a material forming said first. interconnection pattern being smaller than the resistivity of tungsten silicide, said second interconnection pattern being thinner than said third interconnection pattern, and said signal line and said power supply line extending in the same direction wherein the signal line extends above the power supply line with no intervening conductive line therebetween.

Claim 10

The semiconductor integrated circuit according to claim 7 , further comprising: a contact electrode coupled to said power supply line and formed by said third interconnection pattern; a local line formed by said first interconnection pattern and coupled between said contact electrode and said logic circuit, for supplying said power supply potential to said logic circuit.

Claim 11

The semiconductor integrated circuit according to claim 7 , further comprising: a local line formed by said first interconnection pattern and connected to said signal line via a through hole provided in said prescribed area, for transmitting said signal to said logic circuit.

Claim 12

The semiconductor integrated circuit according to claim 7 , further comprising: a signal line for transmitting a signal between said logic circuit and other circuit, said signal line formed by a third interconnection pattern provided above said second interconnection pattern, said signal line provided outside said prescribed area; a local line formed by said first interconnection pattern, extended outside said prescribed area, and connected to said signal line via a through hole provided outside said prescribed area, for transmitting said signal to said logic circuit.

Claim 13

The semiconductor integrated circuit according to claim 7 , wherein said local line is formed of tungsten, and said signal line and power supply line are formed of aluminum.

Claim 14

The semiconductor device according to claim 7 , wherein: said prescribed area is defined by first substantially parallel sides extending in a first direction and second substantially parallel sides, shorter than the first substantially parallel sides, extending in a second direction substantially perpendicular to the first direction; said local line extends substantially parallel to the second direction; and said signal line and said power supply line extend substantially parallel to the first direction.

Claim 15

A semiconductor integrated circuit formed on a semiconductor substrate, comprising: a plurality of semiconductor element groups provided on a surface of said semiconductor substrate, each performing a prescribed operation; a first interconnection pattern provided above said plurality of semiconductor element groups, used as a local line for connecting semiconductor elements in each of said semiconductor element groups; a second interconnection pattern provided above said first interconnection pattern; a third interconnection pattern provided above said second interconnection pattern; and a memory array region including a plurality of memory cells arranged in rows and columns on a surface of said semiconductor substrate, and a plurality of bit line pairs corresponding to said columns of the memory cells respectively, said first interconnection pattern being used as said bit line pairs, and thinner than said second interconnection pattern, said second interconnection pattern being thinner than said third interconnection pattern, wherein said second interconnection pattern is used as a lower layer power supply line for applying a power supply potential to each of said semiconductor element groups; said third interconnection pattern is used as an upper layer signal line for signal input/output between each of said semiconductor element groups and a portion in the substrate other than the semiconductor element group; the lower layer power supply line and the upper layer signal line extend parallel to each other; the local line extends orthogonal to the lower layer power supply line and upper layer signal line; said third interconnection pattern is further used as a contact electrode for connecting said lower layer power supply line with each of said semiconductor element groups; and with no intervening conductive pattern between the lower layer power supply line and the third interconnection pattern.

Claim 16

A semiconductor integrated circuit formed on a semiconductor substrate, comprising: a plurality of semiconductor element groups provided on a surface of said semiconductor substrate, each performing a prescribed operation; a first interconnection pattern provided above said plurality of semiconductor element groups, used as a local line for connecting semiconductor elements in each of said semiconductor element groups; a second interconnection pattern provided above said first interconnection pattern; a third interconnection pattern provided above said second interconnection pattern; and a memory array region including a plurality of memory cells arranged in rows and columns on a surface of said semiconductor substrate, and a plurality of bit line pairs corresponding to said columns of the memory cells respectively, said first interconnection pattern being used as said bit line pairs, and thinner than said second interconnection pattern, said second interconnection pattern being thinner than said third interconnection pattern, wherein said second interconnection pattern is used as a lower layer power supply line for applying a power supply potential to each of said semiconductor element groups; said third interconnection pattern is used as an upper layer signal line for signal input/output between each of said semiconductor element groups and a portion in the substrate other than the semiconductor element group; the lower layer power supply line and the upper layer signal line extend parallel to each other; the local line extends orthogonal to the lower layer power supply line and upper layer signal line; said third interconnection pattern is further used as a contact electrode for connecting said lower layer power supply line with each of said semiconductor element groups; and with no intervening conductive pattern between the lower layer power supply line and the third interconnection pattern.

Claim 17

The semiconductor integrated circuit according to claim 13 , wherein said first, second and third interconnection patterns are formed of aluminum.

Claim 18

The semiconductor integrated circuit according to claim 13 , wherein said first interconnection pattern is formed of a metal having high melting point, and said second and third interconnection patterns are formed of aluminum.

Claim 19

The semiconductor device according to claim 13 , wherein the high melting point metal is tungsten.

Claim 20

The semiconductor integrated circuit according to claim 13 , wherein each of said plurality of semiconductor element groups includes a plurality of semiconductor elements of first and second conductivity types, and said first interconnection pattern connects the semiconductor elements of said first conductivity type in each of said semiconductor element groups.

Claim 21

The semiconductor integrate circuit according to claim 13 , wherein: said plurality of semiconductor element groups are formed in a region defined by first substantially parallel sides extending in a first direction and second substantially parallel sides, shorter than the first sides, extending in a second direction substantially perpendicular to the first direction; said local line extends substantially parallel to the second direction; said lower layer power supply line extends substantially parallel to the first direction; and said upper layer signal line extends substantially parallel to the first direction.