US5355004A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit device having wiring for clock signal supply
Assignee: Renesas Electronics Corp
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Filing: 1992-11-12
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Granted: 1994-10-11
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Expires: 2012-11-12
Abstract
Abstract A semiconductor integrated circuit device wherein terminals other than clock signal terminals in circuit blocks are connected via a first wiring layer to a clock signal source and only the clock signal terminals in the blocks are connected via a second wiring layer to the source. The second wiring layer is formed above the first wiring layer and is connected to the clock signal terminals. Since the second wiring layer is dedicated to the clock signal, clock signal wiring can be laid out as desired when a layout is designed by a hierarchical design technique. There is no chance that propagation characteristics of the clock signals to the blocks deviates, and a cell area can be reduced. Preferably, a third wiring layer connected to the second wiring layer is furthermore provided for dedication to the clock signal.
Inventors
- 👤 Mutsuo Saitoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 21:07
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
185 words
A semiconductor integrated circuit device comprising: a plurality of circuit blocks each having a first terminal to which a clock signal is supplied and a second terminal through which a signal other than said clock signal is sent; a first wiring pattern electrically connected to said second terminals in said plurality of circuit blocks, said first wiring pattern being disposed in a first plane of said device; and a second wiring pattern electrically connected to said first terminals in said plurality of circuit blocks, said second wiring pattern being electrically insulated from said first wiring pattern and disposed in a second plane of said device, said second plane being above said first plane in said device; said clock signal being supplied through said second wiring pattern and said first terminals to said plurality of said circuit blocks; each of said circuit blocks having a third wiring pattern connected to said first terminals and disposed in a third plane of said device which is below said first plane; and said third wiring pattern does not extend outside of an individually associated one of said circuit blocks.
Claim 2
Dependent Claim
185 words
A semiconductor integrated circuit device comprising: a plurality of circuit blocks each having a first terminal to which a clock signal is supplied and a second terminal through which a signal other than said clock signal is sent; a first wiring pattern electrically connected to said second terminals in said plurality of circuit blocks, said first wiring pattern being disposed in a first plane of said device; and a second wiring pattern electrically connected to said first terminals in said plurality of circuit blocks, said second wiring pattern being electrically insulated from said first wiring pattern and disposed in a second plane of said device, said second plane being above said first plane in said device; said clock signal being supplied through said second wiring pattern and said first terminals to said plurality of said circuit blocks; each of said circuit blocks having a third wiring pattern connected to said first terminals and disposed in a third plane of said device which is below said first plane; and said third wiring pattern does not extend outside of an individually associated one of said circuit blocks.
Claim 3
Dependent Claim
21 words
The semiconductor integrated circuit device as claimed in claim 1, wherein said third wiring pattern is made of a polysilicon layer.
Claim 4
Dependent Claim
22 words
The semiconductor integrated circuit device as claimed in claim 2, wherein said polysilicon layer is a gate electrode of an MOS transistor.
Claim 5
Dependent Claim
182 words
A semiconductor integrated circuit device comprising: a plurality of circuit blocks each having a first terminal to which a clock signal is supplied and a second terminal through which a signal other than said clock signal is sent; a first wiring pattern electrically connected to said second terminals in said plurality of circuit blocks, said first wiring pattern being disposed in a first plane of said device; a second wiring pattern electrically connected to said first terminals in said plurality of circuit blocks, said second wiring pattern being electrically insulated from said first wiring pattern and disposed in a second plane of said device, said second plane being above said first plane in said device; said clock signal being supplied through said second wiring pattern and said first terminals to said plurality of said circuit blocks; each of said circuit blocks having a third wiring pattern connected to said first terminals and is disposed in a third plane of said device which is below said first plane; and said third wiring pattern of said circuit blocks are not connected to each other.
Claim 6
Dependent Claim
182 words
A semiconductor integrated circuit device comprising: a plurality of circuit blocks each having a first terminal to which a clock signal is supplied and a second terminal through which a signal other than said clock signal is sent; a first wiring pattern electrically connected to said second terminals in said plurality of circuit blocks, said first wiring pattern being disposed in a first plane of said device; a second wiring pattern electrically connected to said first terminals in said plurality of circuit blocks, said second wiring pattern being electrically insulated from said first wiring pattern and disposed in a second plane of said device, said second plane being above said first plane in said device; said clock signal being supplied through said second wiring pattern and said first terminals to said plurality of said circuit blocks; each of said circuit blocks having a third wiring pattern connected to said first terminals and is disposed in a third plane of said device which is below said first plane; and said third wiring pattern of said circuit blocks are not connected to each other.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-10-10 | 1998-04-11 | 1998-10-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-10-10 | 2002-04-11 | 2002-10-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-10-10 | 2006-04-11 | 2006-10-11 | $7700.00 | Window Closed / Lapsed |