US6400226B2
Expired / Lapsed
US
⏱️ 0.0 years remaining
Distributed amplifier with improved flatness of frequency characteristic
Assignee: Fujitsu Ltd
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Filing: 2000-11-30
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Granted: 2002-06-04
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Expires: 2020-11-30
Abstract
Abstract FETs 31 to 34 for amplification are connected between an input transmission line 10 and an output transmission line 20. A terminating circuit 29 having a capacitor 292 and a terminating resistor 291 connected in series is connected to an end of the output transmission line 20. To improve a flatness of the gain over a low frequency band, a series-connected circuit having a capacitor 71 and a resistor 61 between the gate of each FET and ground, wherein the design parameter of this circuit is determined so that the impedance thereof is lower in the low frequency band but higher in a high frequency band than the input impedance of each FET.
Inventors
- 👤 Masaru Sato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 17:01
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/60; H03F3/605; H03F3/607
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
140 words
A distributed amplifier comprising: an input transmission line; an output transmission line; a terminating circuit, connected to said output transmission line, including a first capacitance and a first resistor connected in series to each other; a plurality of amplifier circuits connected between said input and output transmission lines, each amplifier circuit including a transistor for amplification, said transistor having a control input coupled to said input transmission line; and a plurality of series-connected circuits, provided for respective said amplifier circuits, each including a second capacitor and a second resistor connected in series to each other between said control input of said corresponding transistor and a reference potential, each having impedance lower than an input impedance of said transistor in a frequency band lower than a frequency, but higher than said input impedance in a frequency band higher than said frequency.
Claim 2
Dependent Claim
140 words
A distributed amplifier comprising: an input transmission line; an output transmission line; a terminating circuit, connected to said output transmission line, including a first capacitance and a first resistor connected in series to each other; a plurality of amplifier circuits connected between said input and output transmission lines, each amplifier circuit including a transistor for amplification, said transistor having a control input coupled to said input transmission line; and a plurality of series-connected circuits, provided for respective said amplifier circuits, each including a second capacitor and a second resistor connected in series to each other between said control input of said corresponding transistor and a reference potential, each having impedance lower than an input impedance of said transistor in a frequency band lower than a frequency, but higher than said input impedance in a frequency band higher than said frequency.
Claim 3
Dependent Claim
25 words
The distributed amplifier of claim 1 , wherein a bias voltage is applied to said control inputs of said transistors through respective said second resistors.
Claim 4
Dependent Claim
43 words
The distributed amplifier of claim 2 , wherein each of said transistors is a field effect transistor having a gate electrode as said control input, a drain electrode coupled to said output transmission line, and a source electrode applied with said reference potential.
Claim 5
Dependent Claim
32 words
The distributed amplifier of claim 3 , wherein each of said amplifier circuits further comprises a transistor cascoded to said corresponding transistor and connected between this transistor and said output transmission line.
Claim 6
Dependent Claim
18 words
The distributed amplifier of claim 3 , wherein each of said field effect transistors has a dual gate.
Claim 7
Dependent Claim
43 words
The distributed amplifier of claim 1 , wherein each of said transistors is a field effect transistor having a gate electrode as said control input, a drain electrode coupled to said output transmission line, and a source electrode applied with said reference potential.
Claim 8
Dependent Claim
32 words
The distributed amplifier of claim 6 , wherein each of said amplifier circuits further comprises a transistor cascoded to said corresponding transistor and connected between this transistor and said output transmission line.
Claim 9
Dependent Claim
18 words
The distributed amplifier of claim 6 , wherein each of said field effect transistors has a dual gate.
Claim 10
Dependent Claim
141 words
A semiconductor integrated circuit comprising: an input transmission line; an output transmission line; a terminating circuit, connected to said output transmission line, including a first capacitance and a first resistor connected in series to each other; a plurality of amplifier circuits connected between said input and output transmission lines, each amplifier circuit including a transistor for amplification, said transistor having a control input coupled to said input transmission line; and a plurality of series-connected circuits, provided for respective said amplifier circuits, each including a second capacitor and a second resistor connected in series to each other between said control input of said corresponding transistor and a reference potential, each having impedance lower than an input impedance of said transistor in a frequency band lower than a frequency, but higher than said input impedance in a frequency band higher than said frequency.
Claim 11
Dependent Claim
141 words
A semiconductor integrated circuit comprising: an input transmission line; an output transmission line; a terminating circuit, connected to said output transmission line, including a first capacitance and a first resistor connected in series to each other; a plurality of amplifier circuits connected between said input and output transmission lines, each amplifier circuit including a transistor for amplification, said transistor having a control input coupled to said input transmission line; and a plurality of series-connected circuits, provided for respective said amplifier circuits, each including a second capacitor and a second resistor connected in series to each other between said control input of said corresponding transistor and a reference potential, each having impedance lower than an input impedance of said transistor in a frequency band lower than a frequency, but higher than said input impedance in a frequency band higher than said frequency.
Claim 12
Dependent Claim
19 words
The semiconductor integrated circuit of claim 9 , wherein said semiconductor integrated circuit is a monolithic microwave integrated circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2005-06-03 | 2005-12-03 | 2006-06-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2009-06-03 | 2009-12-03 | 2010-06-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2013-06-03 | 2013-12-03 | 2014-06-04 | $7700.00 | Window Closed / Lapsed |