US6049250A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dittributed feed back distributed amplifier
Assignee: Northrop Grumman Systems Corp
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Filing: 1998-04-03
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Granted: 2000-04-11
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Expires: 2018-04-03
Abstract
Abstract A distributed amplifier topology with distributed feedback includes a plurality of amplifier stages, each of which includes a FET, MESFET or HEMT. A negative feedback network is provided with each amplifier stage which enables the gain of the distributed amplifier to be reduced by varying the negative feedback. An important aspect of the invention relates to the fact that the gain can be varied with virtually no affect on the bandwidth performance of the product and without significantly affecting the return loss, IP3 and noise figure performance of the device.
Inventors
- 👤 Mark Kintis
- 👤 Petar Tomasevic
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 07:02
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/60; H03F3/605; H03F3/607
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
183 words
A distributed amplifier topology comprising: an input terminal; one or more input transmission lines coupled to said input terminal; an output terminal; one or more output transmission lines coupled to said output terminal; one or more amplifier stages coupled between said one or more input transmission lines and said one or more output transmission lines; each amplifier stage including at least one field effect type transistor having gate, drain and source terminals, said field effect type transistor connected in a common source configuration, each amplifier stage further including a capacitor coupled to said gate of said field effect type transistor, said capacitor configured to form a voltage divider with the gate to source capacitance of said field effect transistor in order to reduce the gain of the amplifier stage, at least one amplifier stage including a negative feedback network; means for biasing a plurality of said distributed amplifier stages, said biasing means coupled to said gate terminal and said capacitor; an input line termination impedance coupled to said input transmission line; and an output line termination impedance coupled to said output transmission line.
Claim 2
Dependent Claim
183 words
A distributed amplifier topology comprising: an input terminal; one or more input transmission lines coupled to said input terminal; an output terminal; one or more output transmission lines coupled to said output terminal; one or more amplifier stages coupled between said one or more input transmission lines and said one or more output transmission lines; each amplifier stage including at least one field effect type transistor having gate, drain and source terminals, said field effect type transistor connected in a common source configuration, each amplifier stage further including a capacitor coupled to said gate of said field effect type transistor, said capacitor configured to form a voltage divider with the gate to source capacitance of said field effect transistor in order to reduce the gain of the amplifier stage, at least one amplifier stage including a negative feedback network; means for biasing a plurality of said distributed amplifier stages, said biasing means coupled to said gate terminal and said capacitor; an input line termination impedance coupled to said input transmission line; and an output line termination impedance coupled to said output transmission line.
Claim 3
Dependent Claim
23 words
The distributed amplifier topology as recited in claim 1, wherein at least one of said one or more amplifier stages includes a FET.
Claim 4
Dependent Claim
23 words
The distributed amplifier topology as recited in claim 1, wherein at least one of said one or more amplifier stages includes a MESFET.
Claim 5
Dependent Claim
30 words
The distributed amplifier topology as recited in claim 1, wherein at least one of said one or more amplifier stages includes a HEMT defining a source, gate and drain terminal.
Claim 6
Dependent Claim
16 words
The distributed amplifier topology as recited in claim 1, wherein said negative feedback network is resistive.
Claim 7
Dependent Claim
25 words
The distributed amplifier topology as recited in claim 5, wherein said negative feedback network includes a source resistor, coupled between said source terminal and ground.
Claim 8
Dependent Claim
26 words
The distributed amplifier topology as recited in claim 6, wherein said negative feedback network further includes a feedback resistor coupled between said drain and gate terminals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-04-11 | 2003-10-11 | 2004-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-04-11 | 2007-10-11 | 2008-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-04-11 | 2011-10-11 | 2012-04-11 | $7700.00 | Window Closed / Lapsed |