Step adjustable distributed amplifier network structure

Claim 1

An incrementally adjustable distributed network arrangement including a signal delay line connected to an input signal (E) and an output delay line providing a signal output (A), the arrangement comprising delay elements (Z Gm , Z Dm , mε {1, . . . , n+1}) and a number of controlled sources (T 1 . . . T n ; VCCS), connected together to form a distributed amplifier responsive to a signal input (E) and providing a signal output (A), the distributed amplifier comprising: (a) the number of controlled sources (VCCS) being selected to produce a predetermined level of amplification and each controlled source being individually switched to turn-on or turn-off; (b) a plurality of dual gate FETs (T 1 . . . T n ) comprising said controlled sources, each dual gate FET having a first gate (G 1 ) for receiving the input signal voltage through serially connected delay elements (Z Gm ) forming the input signal delay line, and each dual gate FET having a second gate respectively connected to receive a suitable dc voltage for turning its respective FET on and off; and (c) the dual gate FETs (T 1 . . . T n ) being series connected, the respective first gates of the dual gate FETs (T 1 . . . T n ) being coupled to the input signal delay line of the distributed amplifier, the respective drains of the dual gate FETs (T 1 . . . T n ) being coupled to the output delay line formed by serially connected delay line elements of the distributed amplifier, the respective sources of the dual gate FETs (T 1 . . . T n ) being coupled to a fixed potential, delay elements being coupled between gates of succeeding dual gate FETs and between drains of succeeding dual gate FETs, respectively, the output delay line as well as the signal delay line being respectively terminated with a resistance; and a system of second FETs wherein individual second FETs being disposed in parallel with a corresponding controlled source to form a parallel connected FET in order to avoid impedance transitions during the turning on and off of one or more controlled sources (VCCS), each individual second FET having a first gate (G 1 ) that is connected to a fixed potential and a second gate (G m ) that is at a switching voltage at which no current flows in the system of second FETs with the parallel connected FET, when applied signal voltage input, is active, and that this second FET system is active when there is no current flow in the parallel connected FET transistor that is provided with signal voltage.